Abstract: An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.

Abstract: The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

Abstract: The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode of operation instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less leakage current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.

Abstract: A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry (24) shares the same power supplies VDDA and/or VSSA of the memory array (22) such that during sleep/data retention mode the voltage across both the portion (25, 28) of the periphery circuitry (24) and the memory array (22) of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained. A sequence for powering up and shutting down portions of the periphery circuitry (24) and the external circuitry (26) is also provided.

Abstract: The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

Abstract: A static logic circuit with a pull-up network (155) and a pull-down network (160). The network is fabricated on SOI substrates and the pull-up network comprises at least one NMOS transistor (115) and the pull down network comprises at least one PMOS transistor (120).

Abstract: The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Abstract: The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Abstract: The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

Abstract: An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to the SRAM array having voltage domains defined by a boundary and (3) a power-down voltage controller coupled to the SRAM array and the peripheral circuitry that separately regulates voltages of the SRAM array and the peripheral circuitry to reduce leakage current of the SRAM array and the peripheral circuitry at the boundary during a sleep mode.

Abstract: An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSB to the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.

Abstract: An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSB to the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.

Abstract: An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to the SRAM array having voltage domains defined by a boundary and (3) a power-down voltage controller coupled to the SRAM array and the peripheral circuitry that separately regulates voltages of the SRAM array and the peripheral circuitry to reduce leakage current of the SRAM array and the peripheral circuitry at the boundary during a sleep mode.

Abstract: A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated circuit. One or more transistors within the integrated circuit are initialized such that a steady-state associated with one or more of the transistors is achieved. A capacitance associated with the portion of the integrated circuit is then measured using the measurement circuit. The portion of the integrated circuit is selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement.

Abstract: The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode of operation instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less leakage current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.

Abstract: The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

Abstract: The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

Abstract: The SOI dynamic logic circuits comprises series and parallel pull-down networks (260) that comprise MOS transistors configured in series or parallel. Each pull down network comprises at least one PMOS transistor (270).

Abstract: A system and associated methodology are disclosed for characterizing soft error or failure rates of electronic circuit elements, where the elements are suitable for use as non-memory peripheral logic in semiconductor memory devices, and where the probability of such soft error or failure rates increases as charge sensitive interconnections or nodes of the elements are exposed to radiation, and as scaling continues and voltages and capacitances are thereby reduced.

Abstract: A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry (24) shares the same power supplies VDDA and/or VSSA of the memory array (22) such that during sleep/data retention mode the voltage across both the portion (25, 28) of the periphery circuitry (24) and the memory array (22) of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained. A sequence for powering up and shutting down portions of the periphery circuitry (24) and the external circuitry (26) is also provided.