Abstract: A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type.

Abstract: A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor (208) has a current path connected between the complementary terminal and a second access terminal (216) and has a second control terminal connected to the first control terminal. A first pass gate (604) has a current path connected between the first access terminal (214) and a third access terminal (XBLT) and has a third control terminal. A second pass gate (606) has a current path connected between the second access terminal (216) and a fourth access terminal (XBLB) and has a fourth control terminal connected to the third control terminal.

Abstract: A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor (208) has a current path connected between the complementary terminal and a second access terminal (216) and has a second control terminal connected to the first control terminal. A multiplex circuit (804) is arranged to apply a first voltage (VDD1) to the first power supply terminal in response to a first state of a select signal (SEL) and to apply a second voltage (VDD2) to the first power supply terminal in response to a second state of a select signal.

Abstract: An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.

Abstract: One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.

Abstract: A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.

Abstract: An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor.

Abstract: A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.

Abstract: Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.

Abstract: One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.

Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.

Abstract: Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port.

Abstract: An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor.

Abstract: The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors (110) located within a common active region, and biasing a terminal (135) between the pair (110) relative to gates (125, 155) of the pair (110) and terminals (130, 160) outlying the pair (110) to obtain a leakage current associated with the pair (110).

Abstract: An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type and are not connected together, where each node in the first storage node set is connected to a port in the first port set, where each node in the second storage node set is connected to a port in the second port set, where each of the other nodes is connected to one of the other ports, and where each of the other ports is connected to one and only one of

Abstract: A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type.

Abstract: The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

Abstract: The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

Abstract: The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors (110) located within a common active region, and biasing a terminal (135) between the pair (110) relative to gates (125, 155) of the pair (110) and terminals (130, 160) outlying the pair (110) to obtain a leakage current associated with the pair (110).

Abstract: An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.