Patents by Inventor Xile Yang

Xile Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12367614
    Abstract: Methods and compression units for compressing a block of image data, the block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values, the method comprising: compressing a first data set comprising all or a portion of the two-dimensional block of first values in accordance with a first fixed-length compression algorithm to generate a first compressed block by: identifying common base information for the first data set; and identifying a fixed-length parameter for each first value in the first data set, the fixed-length parameter being zero, one or more than one bits in length; and forming a compressed block for the block of image data based on the first compressed block.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: July 22, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 12367633
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: July 22, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 12354207
    Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M to generate rendered images of the plurality of tiles M. The fragment processing system includes a post-processing module configured to start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: July 8, 2025
    Inventors: Xile Yang, Hai Ao
  • Patent number: 12333641
    Abstract: A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. The multiple byte data is divided into individual bytes and bytes with corresponding byte positions relating to each vertex are grouped together to form a plurality of byte blocks.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: June 17, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 12322026
    Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M and generate rendered images of the plurality of tiles M, where the fragment processing system includes a post-processing module configured to: start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: June 3, 2025
    Assignee: INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD.
    Inventors: Xile Yang, Hai Ao
  • Patent number: 12322005
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: June 3, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Patent number: 12322024
    Abstract: Data structures, methods and primitive block generators for storing primitives in a graphics processing system.
    Type: Grant
    Filed: December 17, 2022
    Date of Patent: June 3, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 12322025
    Abstract: A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Geometry data for the render is received, the geometry data including primitives associated with one or more vertex shader programs. The geometry data is processed using the vertex shader programs to generate processed primitives, and it is determined in which tile each of the processed primitives are located. For at least one selected tile there is stored i) a representation of per-tile vertex shader data identifying the one or more vertex shader programs used to generate the processed primitives in that tile, and ii) a representation of per-tile render data that can be used when rendering the processed primitives in that tile in subsequent stages of the graphics pipeline.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: June 3, 2025
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Xile Yang, Maurizio Zucchelli
  • Publication number: 20250173955
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Application
    Filed: January 18, 2025
    Publication date: May 29, 2025
    Inventors: Xile YANG, Robert BRIGG, John W. HOWSON
  • Patent number: 12315066
    Abstract: A graphics processing method and system are disclosed. The system includes multiple cores with a master mode core and at least one slave mode core, where the master mode core is configured to construct primitives according to input geometry data, split the constructed primitives into primitive core groups, and distribute the primitive core groups to the master mode core and the at least one slave mode core; and the master mode core and the at least one slave mode core are configured to process the distributed primitive core groups to obtain a rendered image. The system and method of the present disclosure provide powerful parallel data processing capability, which allows for processing of a massive amount of geometry data, and enable excellent performance by taking actual working states of hardware into full consideration.
    Type: Grant
    Filed: March 25, 2023
    Date of Patent: May 27, 2025
    Inventors: Xile Yang, Hai Ao
  • Publication number: 20250166276
    Abstract: A control stream decoder decodes a control stream for a tile group comprising at least two tiles of a rendering space. A primitive block entry analyser received a primitive block entry of the control stream and identifies a location in memory of a control data block for a corresponding primitive block. For the received primitive block entry, in response to determining that a current tile is a valid tile for the corresponding primitive block, the control data block for the corresponding primitive block is retrieved from the identified location in memory. An address of the corresponding primitive block in memory is identified from the control data block and primitives of that primitive block relevant for rendering the current tile, and information identifying the address of the corresponding primitive block and the primitives of that primitive block relevant for rendering the current tile is outputted.
    Type: Application
    Filed: January 18, 2025
    Publication date: May 22, 2025
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Patent number: 12293448
    Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: May 6, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20250124642
    Abstract: A graphics processing system renders primitives using a rendering space which is sub-divided into a plurality of regions. Geometry processing logic performs a geometry processing phase for a current render wherein for each region in the plurality of regions it is determined, for each of a plurality of primitives which are present in the region, whether the primitive totally covers the region, and total coverage data is stored indicating which of the primitives which are present in the region totally cover the region. Rendering logic performs, after the geometry processing logic has completed the geometry processing phase for the current render, a rendering phase for each of the regions of the plurality of regions on a region-by-region basis for the current render using the total coverage data for the region.
    Type: Application
    Filed: November 26, 2024
    Publication date: April 17, 2025
    Inventors: Xile Yang, Robert Brigg
  • Patent number: 12266044
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Grant
    Filed: December 31, 2023
    Date of Patent: April 1, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Patent number: 12229878
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: February 18, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Publication number: 20250054097
    Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
  • Publication number: 20250037316
    Abstract: A method of performing lossy compression on a block of image data in accordance with a multi-level difference table determines an origin value for the block of image data, and determines a level within the multi-level difference table for the block of image data, by determining a maximum difference between the determined origin value and any one of image element values in the block of image data and selecting from the multi-level difference table the level whose largest entry most closely represents the determined maximum difference. For each image element value in the block, one of the entries at the determined level within the multi-level difference table is selected, and a compressed block of data for the block of image data is formed, the compressed block of data including (i) data representing the determined origin value, (ii) an indication of the determined level, and (iii) for each image element value in the block of image data, an indication of the selected entry for that image element value.
    Type: Application
    Filed: October 11, 2024
    Publication date: January 30, 2025
    Inventor: Xile Yang
  • Patent number: 12211118
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: January 28, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Patent number: 12154210
    Abstract: Graphics processing renders primitives using a rendering space which is subdivided into a plurality of regions. A geometry processing phase determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region and stores data for the primitives which are determined to totally cover the region to indicate total coverage of the region. A rendering phase retrieves the stored data for the primitives which are present in the region, selectively processes primitives which are present in the region based on the retrieved data to determine which sample points within the region are covered by the primitives, wherein if the retrieved data includes data which indicates total coverage of the region for a particular primitive then the processing determining sample points is skipped; and determines rendered values at the sample points within the region based on the primitives which cover the respective sample points.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: November 26, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Patent number: 12148188
    Abstract: A computer-implemented method and a decompression unit for decompressing a compressed block of data in accordance with a multi-level difference table. The compressed block of data represents a block of image data comprising a plurality of image element values, wherein each level of the multi-level difference table comprises a plurality of entries. An origin value for the block of image data is determined using data representing the origin value from the compressed block of data. A level within the multi-level difference table for the block of image data is identified using an indication of the level from the compressed block of data.
    Type: Grant
    Filed: May 28, 2023
    Date of Patent: November 19, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang