Patents by Inventor Xile Yang

Xile Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135625
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Application
    Filed: December 31, 2023
    Publication date: April 25, 2024
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Publication number: 20240127524
    Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M to generate rendered images of the plurality of tiles M. The fragment processing system includes a post-processing module configured to start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 18, 2024
    Applicant: INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD.
    Inventors: Xile YANG, Hai AO
  • Publication number: 20240127525
    Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M and generate rendered images of the plurality of tiles M, where the fragment processing system includes a post-processing module configured to: start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 18, 2024
    Applicant: INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD.
    Inventors: Xile YANG, Hai AO
  • Patent number: 11954803
    Abstract: A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Lorenzo Belli, Richard Broadhurst
  • Publication number: 20240104833
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Publication number: 20240087216
    Abstract: A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.
    Type: Application
    Filed: November 18, 2023
    Publication date: March 14, 2024
    Inventors: Xile Yang, John W. Howson
  • Publication number: 20240078634
    Abstract: The present disclosure discloses a method and system for processing graphics in tile-based rendering mode by expanding boundaries of tiles. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of expanded tiles M? in screen view space; and a fragment processing system configured to render each expanded tile M? to obtain rendered images of the plurality of expanded tiles M?, and enable a filter kernel to perform pixel filtering according to the rendered image of each expanded tile M?, where the plurality of expanded tiles M? are obtained by dividing the screen view space into a plurality of tiles M and expanding boundaries of the plurality of tiles M respectively. In the present disclosure, the pixel filtering process can be done after rendering of each tile, thereby effectively improving the processing efficiency of pixel filtering.
    Type: Application
    Filed: March 28, 2023
    Publication date: March 7, 2024
    Applicant: INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD.
    Inventors: Xile YANG, Hai AO
  • Patent number: 11922555
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Publication number: 20240070962
    Abstract: A graphics processing method and system are disclosed. The system includes multiple cores with a master mode core and at least one slave mode core, where the master mode core is configured to construct primitives according to input geometry data, split the constructed primitives into primitive core groups, and distribute the primitive core groups to the master mode core and the at least one slave mode core; and the master mode core and the at least one slave mode core are configured to process the distributed primitive core groups to obtain a rendered image. The system and method of the present disclosure provide powerful parallel data processing capability, which allows for processing of a massive amount of geometry data, and enable excellent performance by taking actual working states of hardware into full consideration.
    Type: Application
    Filed: March 25, 2023
    Publication date: February 29, 2024
    Applicant: INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD.
    Inventors: Xile YANG, Hai AO
  • Patent number: 11915455
    Abstract: Methods and compression units for compressing a block of image data, the block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values, the method comprising: compressing a first data set comprising all or a portion of the two-dimensional block of first values in accordance with a first fixed-length compression algorithm to generate a first compressed block by: identifying common base information for the first data set; and identifying a fixed-length parameter for each first value in the first data set, the fixed-length parameter being zero, one or more than one bits in length; and forming a compressed block for the block of image data based on the first compressed block.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 11915363
    Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block.
    Type: Grant
    Filed: May 28, 2023
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Publication number: 20240037693
    Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 1, 2024
    Inventor: Xile Yang
  • Patent number: 11861782
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 2, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Publication number: 20230410427
    Abstract: A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Geometry data for the render is received, the geometry data including primitives associated with one or more vertex shader programs. The geometry data is processed using the vertex shader programs to generate processed primitives, and it is determined in which tile each of the processed primitives are located. For at least one selected tile there is stored i) a representation of per-tile vertex shader data identifying the one or more vertex shader programs used to generate the processed primitives in that tile, and ii) a representation of per-tile render data that can be used when rendering the processed primitives in that tile in subsequent stages of the graphics pipeline.
    Type: Application
    Filed: March 31, 2023
    Publication date: December 21, 2023
    Inventors: John W. Howson, Xile Yang, Maurizio Zucchelli
  • Publication number: 20230401780
    Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 14, 2023
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20230401778
    Abstract: A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Primitives are received that were processed by a geometry processing stage of the graphics pipeline and these are grouped into one or more sets, and a primitive block generated from each set. Primitive block data is stored characterising the content of the one or more primitive blocks. It is determined which tile each of the primitives are located in, and for at least one selected tile a per-tile primitive block list is stored indicating which of the one or more primitive blocks contain primitives located in that tile. It is determined whether the output of a previous render for the selected tile(s) can be used as an output for the render based on the per-tile primitive block list and the primitive block data for the primitive blocks indicated therein, and corresponding data from the previous render.
    Type: Application
    Filed: March 31, 2023
    Publication date: December 14, 2023
    Inventors: John W. Howson, Xile Yang, Maurizio Zucchelli
  • Patent number: 11842435
    Abstract: Methods and tiling engines for storing tiling primitives in a graphics processing system.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: December 12, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 11836849
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Publication number: 20230385981
    Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
  • Patent number: 11823324
    Abstract: A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: November 21, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson