Patents by Inventor Xile Yang

Xile Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12682556
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: July 14, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Publication number: 20260170749
    Abstract: A tiling unit assigning primitives to tiles in a graphics processing system which has rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.
    Type: Application
    Filed: February 6, 2026
    Publication date: June 18, 2026
    Inventor: Xile Yang
  • Publication number: 20260154851
    Abstract: Methods and compression units for compressing a two-dimensional block of image element values. A block of image element values is compressed using a fixed-length compression scheme to form a block of compressed image element values, which are divided into a plurality of sub-blocks of compressed image element values. A pattern of a plurality of patterns formed by the compressed image element values of a first sub-block of the plurality of sub-blocks is identified, and a compressed block of compressed image element values is formed by encoding the first sub-block in the compressed block of compressed image element values with: (i) information identifying the identified pattern, and (ii) the compressed image element values of the first sub-block forming the identified pattern.
    Type: Application
    Filed: January 27, 2026
    Publication date: June 4, 2026
    Inventor: Xile Yang
  • Patent number: 12573132
    Abstract: A tiling unit assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: March 10, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 12561842
    Abstract: Methods and compression units for compressing a two-dimensional block of image element values. The method includes: dividing the two-dimensional block of image element values into a plurality of sub-blocks of image element values; identifying which pattern of a plurality of patterns is formed by the image element values of a first sub-block of the plurality of sub-blocks; and forming a compressed block of image element values by encoding the first sub-block in the compressed block of image element values with: (i) information identifying the pattern, and (ii) the image element values of the first sub-block forming the pattern.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: February 24, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Publication number: 20260038187
    Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.
    Type: Application
    Filed: October 10, 2025
    Publication date: February 5, 2026
    Inventors: Xile Yang, John W. Howson, Jonathan Redshaw
  • Patent number: 12475648
    Abstract: A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.
    Type: Grant
    Filed: April 8, 2024
    Date of Patent: November 18, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Lorenzo Belli, Richard Broadhurst
  • Publication number: 20250349037
    Abstract: Methods and compression units for compressing a block of image data, the block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values, the method comprising: compressing a first data set comprising all or a portion of the two-dimensional block of first values in accordance with a first fixed-length compression algorithm to generate a first compressed block by: identifying common base information for the first data set; and identifying a fixed-length parameter for each first value in the first data set, the fixed-length parameter being zero, one or more than one bits in length; and forming a compressed block for the block of image data based on the first compressed block.
    Type: Application
    Filed: July 22, 2025
    Publication date: November 13, 2025
    Inventor: Xile Yang
  • Publication number: 20250349063
    Abstract: A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. For a selected tile of a plurality of tiles, a representation of per-tile vertex shader data identifying vertex shader programs used to generate processed primitives located within the selected tile is stored, and it is determined whether the output of a previous render for the selected tile can be used as an output for the render, by comparing the per-tile vertex shader data of the selected tile of the render with that of the previous render.
    Type: Application
    Filed: June 2, 2025
    Publication date: November 13, 2025
    Inventors: John W. Howson, Xile Yang, Maurizio Zucchelli
  • Publication number: 20250349064
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system. A multi-level hierarchy of tile groups is generated, each level comprising one or more tile groups comprising one or more of the plurality of tiles. A plurality of primitive blocks is received, each comprising geometry data for one or more primitives. Each of the plurality of primitive blocks is associated with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile. A control stream is generated for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Application
    Filed: July 22, 2025
    Publication date: November 13, 2025
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 12462464
    Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: November 4, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Jonathan Redshaw
  • Publication number: 20250308127
    Abstract: Data in a processing system is compressed, the data comprising a plurality of values having a same multiple-byte format. Bytes with corresponding byte significance are grouped together to form a plurality of byte blocks, and a byte block of the plurality of byte blocks is compressed using a compression algorithm comprising storing at least one byte from the byte block as a byte origin, and storing at least one remaining byte in the byte block as a difference value from the byte origin.
    Type: Application
    Filed: June 17, 2025
    Publication date: October 2, 2025
    Inventor: Xile Yang
  • Publication number: 20250299415
    Abstract: Data structures, methods and primitive block generators for storing primitives in a graphics processing system. A primitive is added to a primitive block based on at least state data associated with the primitive, the primitive block comprising two or more primitive sections and a state data section, wherein each primitive section comprises data for one or more primitives and has one or more size constraints and wherein each primitive section comprises a primitive data sub-section and a vertex data sub-section, and wherein the state data section comprises information identifying state data common to the one or more primitives for which data is stored in the two or more primitive sections. The primitive block is then stored in memory.
    Type: Application
    Filed: May 2, 2025
    Publication date: September 25, 2025
    Inventor: Xile Yang
  • Patent number: 12423775
    Abstract: The present disclosure discloses a method and system for processing graphics in tile-based rendering mode by expanding boundaries of tiles. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of expanded tiles M? in screen view space; and a fragment processing system configured to render each expanded tile M? to obtain rendered images of the plurality of expanded tiles M?, and enable a filter kernel to perform pixel filtering according to the rendered image of each expanded tile M?, where the plurality of expanded tiles M? are obtained by dividing the screen view space into a plurality of tiles M and expanding boundaries of the plurality of tiles M respectively. In the present disclosure, the pixel filtering process can be done after rendering of each tile, thereby effectively improving the processing efficiency of pixel filtering.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: September 23, 2025
    Inventors: Xile Yang, Hai Ao
  • Publication number: 20250265673
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Application
    Filed: May 6, 2025
    Publication date: August 21, 2025
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Publication number: 20250265764
    Abstract: Graphics processing systems render items of geometry using a rendering space subdivided into a plurality of first regions. The items of geometry are stored in data blocks having a respective block ID. The items of geometry are rendered within a second region of a plurality of second regions using a first control list for the first region of which the second region is a part, and a second control list for the second region, each control list comprising entries associated with respective items of geometry, each of the entries comprising a block ID associated with a data block. The items of geometry are rendered within the second region by choosing from the first control list and the second list, the entry comprising the lowest block ID which has not previously been chosen, and fetching items of geometry from the data block associated with the block ID of the chosen entry.
    Type: Application
    Filed: May 6, 2025
    Publication date: August 21, 2025
    Inventors: Xile Yang, Robert Brigg
  • Patent number: 12367614
    Abstract: Methods and compression units for compressing a block of image data, the block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values, the method comprising: compressing a first data set comprising all or a portion of the two-dimensional block of first values in accordance with a first fixed-length compression algorithm to generate a first compressed block by: identifying common base information for the first data set; and identifying a fixed-length parameter for each first value in the first data set, the fixed-length parameter being zero, one or more than one bits in length; and forming a compressed block for the block of image data based on the first compressed block.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: July 22, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 12367633
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: July 22, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 12354207
    Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M to generate rendered images of the plurality of tiles M. The fragment processing system includes a post-processing module configured to start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: July 8, 2025
    Inventors: Xile Yang, Hai Ao
  • Patent number: 12333641
    Abstract: A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. The multiple byte data is divided into individual bytes and bytes with corresponding byte positions relating to each vertex are grouped together to form a plurality of byte blocks.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: June 17, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang