Patents by Inventor Xile Yang

Xile Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220245755
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Publication number: 20220198745
    Abstract: A tiling unit assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.
    Type: Application
    Filed: January 7, 2022
    Publication date: June 23, 2022
    Inventor: Xile Yang
  • Patent number: 11341601
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Publication number: 20220148125
    Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 12, 2022
    Inventor: Xile Yang
  • Publication number: 20220148255
    Abstract: A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Inventors: Xile Yang, John W. Howson
  • Publication number: 20220122314
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Application
    Filed: October 29, 2021
    Publication date: April 21, 2022
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Publication number: 20220084281
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Patent number: 11263806
    Abstract: A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 1, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson
  • Patent number: 11257181
    Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: February 22, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 11244498
    Abstract: A tiling unit assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 8, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Publication number: 20220028030
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic and rasterization logic. The geometry processing logic includes first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to: divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one of the one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block that are to be used in generating the rendering output.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 27, 2022
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Publication number: 20220012841
    Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
    Type: Application
    Filed: May 28, 2021
    Publication date: January 13, 2022
    Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
  • Patent number: 11217007
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: January 4, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Publication number: 20210407191
    Abstract: A graphics processing unit and method for processing fragments in a graphics processing system which includes: (i) hidden surface removal logic configured to perform hidden surface removal on fragments, and (ii) processing logic configured to execute shader programs for fragments. Initial processing of fragments is performed at the hidden surface removal logic. Some of the fragments have a shader-dependent property. A shader program for a particular fragment having the shader-dependent property is split into two stages. The initial processing comprises performing a depth test on the particular fragment. In response to the particular fragment passing the depth test of the initial processing in the hidden surface removal logic, a first stage, but not a second stage, of the shader program is executed for the particular fragment at the processing logic. The first stage of the shader program has instructions for determining the property of the particular fragment.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 30, 2021
    Inventors: Xile Yang, Christopher Plant
  • Publication number: 20210383598
    Abstract: A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primiti
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Patent number: 11182952
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: November 23, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Publication number: 20210352292
    Abstract: Methods and decompression units for decompressing a selected sub-block of image element values from a compressed block of image element values. The method includes: identifying, from the compressed block of image element values, a pattern of a plurality of patterns of image element values associated with the selected sub-block; identifying, from the compressed block of image element values, one or more image element values associated with the selected sub-block; and generating the selected sub-block from the pattern and the one or more image element values associated with the selected sub-block.
    Type: Application
    Filed: March 30, 2021
    Publication date: November 11, 2021
    Inventor: Xile Yang
  • Publication number: 20210350580
    Abstract: Methods and compression units for compressing a two-dimensional block of image element values. The method includes: dividing the two-dimensional block of image element values into a plurality of sub-blocks of image element values; identifying which pattern of a plurality of patterns is formed by the image element values of a first sub-block of the plurality of sub-blocks; and forming a compressed block of image element values by encoding the first sub-block in the compressed block of image element values with: (i) information identifying the pattern, and (ii) the image element values of the first sub-block forming the pattern.
    Type: Application
    Filed: March 30, 2021
    Publication date: November 11, 2021
    Inventor: Xile Yang
  • Patent number: 11158023
    Abstract: A graphics processing system having a rendering space divided into a plurality of tiles. The system comprises geometry processing logic and rasterization logic. The geometry processing logic is configured to generate transformed position data for each of a plurality of untransformed primitives based on untransformed geometry data associated therewith; group the plurality of untransformed primitives into a plurality of primitive blocks; and generate an untransformed display list for each tile based on the transformed position data. Each untransformed display list comprises: (i) information identifying each untransformed primitive block that comprises at least one untransformed primitive that, when transformed, falls at least partially with the tile; and (ii) for each identified untransformed primitive bock, information identifying the untransformed primitives or transformed primitives related to that untransformed primitive block relevant for rendering the tile.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: October 26, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, Xile Yang, John W. Howson
  • Patent number: 11145025
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic and rasterization logic. The geometry processing logic includes first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to: divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one of the one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block that are to be used in generating the rendering output.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: October 12, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John Howson, Xile Yang