Patents by Inventor Xile Yang

Xile Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230351670
    Abstract: Graphics processing renders primitives using a rendering space which is subdivided into a plurality of regions. A geometry processing phase determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region and stores data for the primitives which are determined to totally cover the region to indicate total coverage of the region. A rendering phase retrieves the stored data for the primitives which are present in the region, selectively processes primitives which are present in the region based on the retrieved data to determine which sample points within the region are covered by the primitives, wherein if the retrieved data includes data which indicates total coverage of the region for a particular primitive then the processing determining sample points is skipped; and determines rendered values at the sample points within the region based on the primitives which cover the respective sample points.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20230351678
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 2, 2023
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Patent number: 11790480
    Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: October 17, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 11790560
    Abstract: Methods and decompression units for decompressing data from a compressed block of image data, the compressed block of image data representing a block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Publication number: 20230316580
    Abstract: A computer-implemented method and a decompression unit for decompressing a compressed block of data in accordance with a multi-level difference table. The compressed block of data represents a block of image data comprising a plurality of image element values, wherein each level of the multi-level difference table comprises a plurality of entries. An origin value for the block of image data is determined using data representing the origin value from the compressed block of data. A level within the multi-level difference table for the block of image data is identified using an indication of the level from the compressed block of data.
    Type: Application
    Filed: May 28, 2023
    Publication date: October 5, 2023
    Inventor: Xile Yang
  • Publication number: 20230298262
    Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block.
    Type: Application
    Filed: May 28, 2023
    Publication date: September 21, 2023
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Patent number: 11741656
    Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20230260074
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 17, 2023
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Patent number: 11727525
    Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 15, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
  • Publication number: 20230252711
    Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.
    Type: Application
    Filed: March 7, 2023
    Publication date: August 10, 2023
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Publication number: 20230245372
    Abstract: A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. The multiple byte data is divided into individual bytes and bytes with corresponding byte positions relating to each vertex are grouped together to form a plurality of byte blocks.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Inventor: Xile Yang
  • Publication number: 20230230319
    Abstract: A graphics processing unit and method for processing fragments in a graphics processing system which includes: (i) hidden surface removal logic configured to perform hidden surface removal on fragments, and (ii) processing logic configured to execute shader programs for fragments. Initial processing of fragments is performed at the hidden surface removal logic. Some of the fragments have a shader-dependent property. A shader program for a particular fragment having the shader-dependent property is split into two stages. The initial processing comprises performing a depth test on the particular fragment. In response to the particular fragment passing the depth test of the initial processing in the hidden surface removal logic, a first stage, but not a second stage, of the shader program is executed for the particular fragment at the processing logic. The first stage of the shader program has instructions for determining the property of the particular fragment.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 20, 2023
    Inventors: Xile Yang, Christopher Plant
  • Patent number: 11699258
    Abstract: Methods and graphics processing systems render primitives using a rendering space which is subdivided into a plurality of regions. Geometry processing logic performs a geometry processing phase which determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region; and stores data for the primitives which are present in the region, wherein the stored data comprises, for each of the primitives which are determined to totally cover the region, data to indicate total coverage of the region. Rendering logic performs a rendering phase for rendering primitives within the region.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: July 11, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20230215095
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 6, 2023
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 11663771
    Abstract: A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primiti
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: May 30, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Patent number: 11663743
    Abstract: There is provided a computer-implemented method and a decompression unit for decompressing a compressed block of data in accordance with a multi-level difference table. The compressed block of data represents a block of image data comprising a plurality of image element values, wherein each level of the multi-level difference table comprises a plurality of entries. An origin value for the block of image data is determined using data representing the origin value from the compressed block of data. A level within the multi-level difference table for the block of image data is identified using an indication of the level from the compressed block of data.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 30, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 11657565
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 23, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Patent number: 11640648
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic and rasterization logic. The geometry processing logic includes first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to: divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one of the one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block that are to be used in generating the rendering output.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: May 2, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Publication number: 20230122999
    Abstract: Data structures, methods and primitive block generators for storing primitives in a graphics processing system.
    Type: Application
    Filed: December 17, 2022
    Publication date: April 20, 2023
    Inventor: Xile Yang
  • Publication number: 20230111561
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley