Patents by Inventor Xin Cheng

Xin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210012302
    Abstract: Provided is a system for constructing mobile electric energy interconnection. The system includes at least one mobile electric energy exchange device, a mobile electric energy interconnection management platform and at least one stationary electric energy interconnection device. The mobile electric energy interconnection management platform is configured to match the at least one mobile electric energy exchange device with the at least one stationary electric energy interconnection device, and push a matching result to the at least one mobile electric energy exchange device and the at least one stationary electric energy interconnection device. Also provided is a method for constructing mobile electric energy interconnection, a data testing method and device, and a computer readable storage medium.
    Type: Application
    Filed: November 30, 2018
    Publication date: January 14, 2021
    Applicants: INFORMATION AND COMMNUNICATION BRANCH, STATE GRID JIANGXI ELECTRIC POWER COMPANY, STATE GRID CORPORATION OF CHINA
    Inventors: Xianming LIU, Chi E, Ming CHENG, Hongjie SHEN, Jun LI, Xin SUN, Zhenwen TAO, Hong JIANG, Bin LI, Jianxu WANG, Zilan ZHOU
  • Patent number: 10886391
    Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material is etched away from the two sacrificial layers in a region of the fin. A gate stack is formed around the active layer in the region. The active layer is etched after forming the gate stack to form a quantum dot.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10886384
    Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Publication number: 20200411371
    Abstract: Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.
    Type: Application
    Filed: March 7, 2019
    Publication date: December 31, 2020
    Inventors: Xin LIU, Fei WANG, Rui CHENG, Abhijit Basu MALLICK, Robert Jan VISSER
  • Publication number: 20200411087
    Abstract: The present invention provides PCM devices with gradual SET and RESET characteristics. In one aspect, a method of forming a PCM computing device includes: forming word lines and an insulating hardmask cap on a substrate; forming a PCM material over the word lines, having a tapered thickness; and forming bit lines over the PCM material, the insulating hardmask cap, and the word lines, wherein the tapered thickness of the PCM material varies gradually between the word lines and the bit lines. The tapered thickness can be formed by depositing a non-conformal layer of the PCM material or by depositing a conformal layer and then tapering the PCM material using a directional etch. A PCM device is also provided.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Inventors: Kangguo Cheng, Xin Miao, Chen Zhang, Wenyu Xu
  • Patent number: 10874125
    Abstract: The invention discloses a method for improving the cooking and eating quality of brown rice by using Lactic acid bacteria fermentation, which belongs to the technical field of food processing. The method comprises the steps of mixing activated lactic acid bacteria with water and brown rice, loading the mixture into a one-way outgassing container, removing excess air or filling up the container, and sealing the container and performing fermentation. The invention is very simple and easy to operate, and has very low energy consumption. It is suitable to be up scaled for industrial production and will significantly promote brown rice to become a staple food.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: December 29, 2020
    Assignee: Jiangnan University
    Inventors: Yongfu Li, Xin Cheng, Feng Shi, Li Wang, Zhengxing Chen, Yanan Li, Ren Wang, Xiaohu Luo, Juan Li
  • Publication number: 20200395467
    Abstract: An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Lan Yu, Xin Miao, Chen Zhang, Heng Wu, Kangguo Cheng
  • Patent number: 10865074
    Abstract: An automatic handrail tensioning system and a method for adjusting the tension degree of a handrail, and belongs to the technical field of escalators. The automatic handrail tensioning system of the present invention comprises: a sensor for detecting information that can reflect a tension degree of the handrail; a controller for determining the tension degree information of the handrail according to the information detected by the sensor, and generating a corresponding control instruction for adjusting the tension degree of the handrail based on the tension degree information; and an actuator for driving a tensioning device to adjust the tension degree of the handrail based on the control instruction.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 15, 2020
    Assignee: OTIS ELEVATOR COMPANY
    Inventors: QingXi Cai, JianGuo Li, Xin Wei, Jie Hu, LiFei Cheng, ZuAn Tang, Jun Ma
  • Publication number: 20200381426
    Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Wenyu Xu, Xin Miao, Chen Zhang, Kangguo Cheng
  • Publication number: 20200368971
    Abstract: In some examples, with respect to three-dimensional printer color management, three-dimensional printer native space coordinates of a three-dimensional printer may be mapped to three-dimensional printer printing agent space coordinates of the three-dimensional printer. The three-dimensional printer printing agent space coordinates may be mapped to color space coordinates. The color space coordinates may be mapped to two-dimensional printer printing agent space coordinates of a two-dimensional printer. The two-dimensional printer printing agent space coordinates may be mapped to two-dimensional printer native space coordinates of the two-dimensional printer. A color management protocol of the two-dimensional printer may be utilized, based on the mapping of the three-dimensional printer native space coordinates to the two-dimensional printer native space coordinates, for the three-dimensional printer to print a three-dimensional object.
    Type: Application
    Filed: December 20, 2017
    Publication date: November 26, 2020
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Miguel Angel LOPEZ ALVAREZ, Morgan T. SCHRAMM, Xin CHENG, Jay s. GONDEK
  • Patent number: 10846556
    Abstract: A vehicle insurance image processing method includes: acquiring a vehicle insurance image; processing the vehicle insurance image by using a preset image classification algorithm, to determine at least one category label of the vehicle insurance image; and storing, based on classification, the vehicle insurance image in a corresponding usage scenario according to the at least one category label.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: November 24, 2020
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Jinlong Hou, Haitao Zhang, Xin Guo, Juan Xu, Jian Wang, Yuan Cheng, Danni Cheng
  • Patent number: 10845248
    Abstract: A method includes directing a first plurality of probe laser pulses through a sample, dividing each of the first plurality of probe laser pulses to generate a first interferogram, and generating first image data reproducible as a first phase image of the sample. A plurality of pump laser bursts are directed onto the sample to heat the sample. A second plurality of probe laser pulses are directed through the sample at a predetermined time delay. Each of the second plurality of probe laser pulses are divided to generate a second interferogram. Second image data is generated that is reproducible as a second phase image of the sample. A transient phase shift is determined in the second phase image relative to the first phase image. A vibrational spectroscopy property is determined of the sample based on the transient phase shift, thereby allowing an identification of chemical bond information of within the sample.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: November 24, 2020
    Assignees: Trustees of Boston University, Purdue Research Foundation
    Inventors: Ji-Xin Cheng, Delong Zhang, Lu Lan
  • Patent number: 10838236
    Abstract: Contact lenses incorporate high plus or add power profiles that at least one of slow, retard or preventing myopia progression and minimize halo effect. The lens includes a center zone with a negative power for myopic vision correction; and at least one treatment zone surrounding the center zone, the at least one treatment zone having a power profile that increases from an outer margin of the center zone to a positive power within the at least one treatment zone of greater than +5.00 D.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 17, 2020
    Assignee: Johnson & Johnson Vision Care, Inc
    Inventors: Noel A. Brennan, Khaled Chehab, Xu Cheng, Michael J. Collins, Manwai Charis Lau, Eric R. Ritchey, Xin Wei
  • Patent number: 10840381
    Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Kangguo Cheng, Michael A. Guillorn, Xin Miao
  • Patent number: 10833073
    Abstract: Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Juntao Li
  • Patent number: 10833158
    Abstract: A technique relates to a semiconductor device. A stack is formed of alternating layers of inserted layers and channel layers on a substrate. Source or drain (S/D) regions are formed on opposite sides of the stack. The inserted layers are converted into oxide layers. Gate materials are formed on the stack.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10833157
    Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Chen Zhang, Xin Miao
  • Patent number: 10833176
    Abstract: A method for forming a semiconductor device comprises forming a fin on a substrate and forming a sacrificial gate over a channel region of the fin. A hydrogen terminated surface is formed on sidewalls of the sacrificial gate, and a spacer is deposited on the hydrogen terminated surface of the sacrificial gate. An insulator layer is formed over portions of the fin. The sacrificial gate is removed to expose the channel region of the fin, and a gate stack is formed over the channel region of the fin.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Publication number: 20200348182
    Abstract: A method includes directing a first plurality of probe laser pulses through a sample, dividing each of the first plurality of probe laser pulses to generate a first interferogram, and generating first image data reproducible as a first phase image of the sample. A plurality of pump laser bursts are directed onto the sample to heat the sample. A second plurality of probe laser pulses are directed through the sample at a predetermined time delay. Each of the second plurality of probe laser pulses are divided to generate a second interferogram. Second image data is generated that is reproducible as a second phase image of the sample. A transient phase shift is determined in the second phase image relative to the first phase image. A vibrational spectroscopy property is determined of the sample based on the transient phase shift, thereby allowing an identification of chemical bond information of within the sample.
    Type: Application
    Filed: May 1, 2020
    Publication date: November 5, 2020
    Inventors: Ji-Xin Cheng, Delong Zhang, Lu Lan
  • Patent number: 10825759
    Abstract: A power module and a production method of the same, wherein a metal substrate is connected with the connection substrate in a high temperature, and in a process of cooling from a high temperature to a low temperature, an upper surface and a lower surface of the metal substrate are bendingly deformed toward the connection substrate, and the upper surface of the metal substrate is formed as a curved surface protruding toward the connection substrate, then the lower surface of the metal substrate is processed into a plane. In the power module and the production method of the disclosure, the second bonding material between the metal substrate and the connection substrate has a larger edge thickness, which reduces the thermal stress that the edge of the second bonding material is subject to, thereby improving the reliability of the power module while the power module has good heat dissipation performance.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 3, 2020
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Wei Cheng, Ganyu Zhou, Xin Zou, Zhenqing Zhao