Patents by Inventor Xin Lin
Xin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8344481Abstract: By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required.Type: GrantFiled: March 7, 2011Date of Patent: January 1, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Bernhard H. Grote, Hongning Yang, Jiang-Kai Zuo
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Publication number: 20120292292Abstract: A feed control method for wire cutting electrochemical discharge machining is disclosed. The method determines whether a contact event has occurred using a wire electrode, based on variations in wire tension when being cut. A wire is cut with an ideal feed speed when the wire electrode is not in contact with a workpiece.Type: ApplicationFiled: July 26, 2012Publication date: November 22, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jui-Kuan Lin, Hsiang-Kuo Lee, Yang-Xin Lin, Hsin-Chuan Su
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Publication number: 20120264270Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.Type: ApplicationFiled: June 27, 2012Publication date: October 18, 2012Applicant: Freescale Semiconductor, Inc.Inventors: XIN LIN, Daniel J. Blomberg, Jiang-Kai Zou
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Publication number: 20120205738Abstract: Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space (52, 152) adjacent the drain (56, 156), is avoided by providing a lightly doped region (511, 1511) of a first conductivity type (CT) separating the first CT drift space (52, 152) from an opposite CT WELL region (53, 153) in which the first CT source (57, 157) is located, and a further region (60, 160) of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region (53, 153) under an edge (591, 1591) of the gate (59, 159) located near a boundary (531, 1531) of the WELL region (53, 153) into the lightly doped region (511, 1511), and a shallow still further region (66, 166) of the first CT Ohmically coupled to the source (57, 157) and ending near the gate edge (591, 159) whereby the effective channel length (61, 161) in the further region (60, 160) is reduced to near zero.Type: ApplicationFiled: February 11, 2011Publication date: August 16, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Hongning Yang, Xin Lin, Jiang-Kai Zuo
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Publication number: 20120187538Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.Type: ApplicationFiled: January 26, 2011Publication date: July 26, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Patent number: 8227861Abstract: A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.Type: GrantFiled: December 22, 2010Date of Patent: July 24, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Hongning Yang, Xin Lin, Jiang-Kia Zuo
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Patent number: 8212292Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.Type: GrantFiled: November 20, 2009Date of Patent: July 3, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kia Zuo
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Patent number: 8208113Abstract: A pixel structure including a substrate, a scan line, a data line, a common line, an active device, a pixel electrode, a passivation layer and a transition auxiliary electrode is provided. The scan line and the data line on the substrate intersect with each other to define a pixel region. The common line on the substrate is parallel to the scan line. The active device disposed within the pixel region is electrically connected to the scan line and the data line. The pixel electrode disposed within the pixel region is electrically connected to the active device. The passivation layer is between the data line and the pixel electrode. The transition auxiliary electrode is adjacent to the periphery of the pixel electrode and electrically connected to the common line through a contact hole of the passivation layer. The transition auxiliary electrode and the pixel electrode are made of the same film.Type: GrantFiled: January 20, 2010Date of Patent: June 26, 2012Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Chih-Chieh Wang, Yao-Hong Chien, Xin-Xin Lin, Li-Shan Chen, Xuan-Yu Liu
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Patent number: 8198703Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.Type: GrantFiled: January 18, 2010Date of Patent: June 12, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Publication number: 20120098096Abstract: A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.Type: ApplicationFiled: October 21, 2010Publication date: April 26, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Bernhard H. Grote, Jiang-Kai Zuo
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Publication number: 20120098095Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.Type: ApplicationFiled: October 20, 2010Publication date: April 26, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
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Patent number: 8134219Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.Type: GrantFiled: June 1, 2011Date of Patent: March 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Publication number: 20120035060Abstract: Described herein are methods and kits useful for the extraction and analysis of genomic DNA from leukoreduced blood or plasma samples.Type: ApplicationFiled: August 3, 2011Publication date: February 9, 2012Applicant: BioArray Solutions, Ltd.Inventors: Xin Lin, Ermelina G. Enriquez
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Publication number: 20110320359Abstract: A secure communication method and device based on application layer for mobile financial service. According to the invention, the exchanged messages in the financial transaction are few, and the requirement for the processing capability of the mobile terminal is low. The invention uses the digital signature technology for information abstract based on asymmetric secret keys, and the integrity of the transaction information is guaranteed and non-repudiation requirement is met. The invention also uses digital envelop technology based on asymmetric secret keys, and the secrecy of the transaction information. The strand space theory proves that the security of the preferred embodiment of the invention can be guaranteed.Type: ApplicationFiled: June 22, 2009Publication date: December 29, 2011Inventors: Dake Li, Jinji Zhao, Xin Lin, Haihui Huang
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Publication number: 20110286990Abstract: The present invention is directed to methods of diagnosing and treating a fibrotic condition in a mammalian subject. These methods involve measuring the levels of trimethylation at lysine residue 27 of histone-3 and/or measuring the expression levels of EZH2 or YY-1. Agents useful for treating fibrosis or a fibrotic condition are also disclosed.Type: ApplicationFiled: November 2, 2009Publication date: November 24, 2011Applicant: UNIVERSITY OF ROCHESTERInventors: Jia Guo, Xin Lin, Steve Georas, Patricia Sime
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Publication number: 20110227135Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Publication number: 20110175199Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.Type: ApplicationFiled: January 18, 2010Publication date: July 21, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Patent number: 7972913Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.Type: GrantFiled: May 28, 2009Date of Patent: July 5, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Publication number: 20110147893Abstract: By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required.Type: ApplicationFiled: March 7, 2011Publication date: June 23, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Bernhard H. Grote, Hongning Yang, Jiang-Kai Zuo
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Publication number: 20110121428Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.Type: ApplicationFiled: November 20, 2009Publication date: May 26, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo