Abstract: A pixel structure including a substrate, a scan line, a data line, a common line, an active device, a pixel electrode, a passivation layer and a transition auxiliary electrode is provided. The scan line and the data line on the substrate intersect with each other to define a pixel region. The common line on the substrate is parallel to the scan line. The active device disposed within the pixel region is electrically connected to the scan line and the data line. The pixel electrode disposed within the pixel region is electrically connected to the active device. The passivation layer is between the data line and the pixel electrode. The transition auxiliary electrode is adjacent to the periphery of the pixel electrode and electrically connected to the common line through a contact hole of the passivation layer. The transition auxiliary electrode and the pixel electrode are made of the same film.

Abstract: An apparatus for processing an image with a discrete wavelet transform is provided. For one-dimensional circuit, the method changes conventional image data processing flow and uses common product of sequential calculations with respect to the time axis. The calculations for input data are not repeated so that components of the hardware architecture are minimized. For two-dimensional circuit, the method uses an external data scanning method to eliminate an external memory, transposing buffer, from a transforming circuit.

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

Abstract: The present invention provides the molecular basis for cytokine induction of NF-&kgr;B-dependent immune and inflammatory responses, emphasizing a role for both NIK-NIK and NIK-IKK protein—protein interactions. A relatively small region of NIK selectively impairs the NIK-IKK interaction. The present invention provides a novel and highly specific method for modulating NF-&kgr;B-dependent immune, inflammatory, and anti-apoptotic responses, based on interruption of the critical protein—protein interaction of NIK and IKK. The present invention provides methods for inhibiting NF-&kgr;B-dependent gene expression, using mutant NIK proteins. One embodiment of the present invention provides kinase-deficient NIK mutant proteins that inhibit activation of IKK. Another embodiment of the invention provides N-terminus NIK mutant proteins that bind IKK, thus inhibiting NIK/IKK interaction.

Abstract: Silicon dioxide thin film have been deposited at temperatures from 25° C. to 250° C. by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. At these temperatures, the PETMS oxide films have been found to exhibit adjustable stress and adjustable conformality. Post deposition annealing in forming gas at or below the deposition temperatures has been shown to be very effective in improving the PETMS oxide properties while preserving the low temperature aspect of the PETMS oxides.

Abstract: Silicon dioxide thin film have been deposited at temperatures from 25° C. to 250° C. by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. At these temperatures, the PETMS oxide films have been found to exhibit adjustable stress and adjustable conformality. Post deposition annealing in forming gas at or below the deposition temperatures has been shown to be very effective in improving the PETMS oxide properties while preserving the low temperature aspect of the PETMS oxides.

Abstract: The present invention provides the molecular basis for cytokine induction of NF-&kgr;B-dependent immune and inflammatory responses, emphasizing a role for both NIK-NIK and NIK-IKK protein-protein interactions. A relatively small region of NIK selectively impairs the NIK-IKK interaction. The present invention provides a novel and highly specific method for modulating NF-&kgr;B-dependent immune, inflammatory, and anti-apoptotic responses, based on interruption of the critical protein-protein interaction of NIK and IKK. The present invention provides methods for inhibiting NF-&kgr;B-dependent gene expression, using mutant NIK proteins. One embodiment of the present invention provides kinase-deficient NIK mutant proteins that inhibit activation of IKK. Another embodiment of the invention provides N-terminus NIK mutant proteins that bind IKK, thus inhibiting NIK/IKK interaction.

Abstract: The present invention provides the molecular basis for cytokine induction of NF-&kgr;B-dependent immune and inflammatory responses, emphasizing a role for both NIK-NIK and NIK-IKK protein-protein interactions. A relatively small region of NIK selectively impairs the NIK-IKK interaction. The present invention provides a highly specific method for modulating NF-&kgr;B-dependent immune, inflammatory, and anti-apoptotic responses, based on interruption of the critical protein-protein interaction of NIK and IKK. The present invention provides methods for inhibiting NF-&kgr;B-dependent gene expression, using mutant NIK proteins. One embodiment of the present invention provides kinase-deficient NIK mutant proteins that inhibit activation of IKK. Another embodiment of the invention provides N-terminus NIK mutant proteins that bind IKK, thus inhibiting NIK/IKK interaction.

Abstract: A polyurethane elastic fiber is prepared from a polyurethane prepolymer by reaction extruding the polyurethane prepolymer and a chain extender, preferably with twin-screw extruder, and melt spinning the resulting polyurethane elastomer from the extrusion. The polyurethane prepolymer is obtained by carrying out a pre-polymerization reaction of a polyester diol and a diisocyanate, wherein the polyester diol comprises two different types of polyol, the first type being poly(tetramethylene adipate) glycol or poly(.epsilon.-caprolactone) glycol and the second type being a reaction product of a diol and dicarboxylic acid having 36 carbon atoms.

Abstract: A method for reducing the field dependence of an off-state current flow condition in a field-effect transistor having a source electrode, a drain electrode and a gate electrode, includes the steps of: applying a far off-state bias between the drain electrode and the gate electrode to drive a conduction channel in the field effect transistor into a far off-state; and applying a far off-state bias between the source electrode and the gate electrode to again drive the conduction channel into a far off-state; wherein both applying steps cause application of the far off-state bias for a sufficient time to reduce gate voltage dependency of off-state current flow in the conduction channel during a period when an off-state potential is applied to the gate electrode.