Patents by Inventor Xing Wei
Xing Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12646005Abstract: Embodiments of the present disclosure relate to methods, systems, and computer program products for optimized prediction of a tree ensemble. According to a method, an input request is received, which indicates a plurality of input values for a plurality of variables associated with a tree ensemble. A plurality of target transformed intervals, into which the plurality of input values fall respectively, are determined by matching the plurality of input values with a plurality of sets of transformed intervals for the plurality of variables respectively. Respective prediction results for a plurality of tree models of the tree ensemble are determined based on the plurality of target transformed intervals and respective node hierarchies of the plurality of tree models. A tree ensemble prediction result is determined for the input request based on the determined prediction results of the plurality of tree models.Type: GrantFiled: November 4, 2021Date of Patent: June 2, 2026Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dong Hai Yu, Jing Xu, Jun Wang, Xing Wei, Lei Tian, Yao Dong Liu
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Publication number: 20260114994Abstract: The present disclosure discloses a prosthetic valve leaflet material, a valve leaflet, a valve, and a preparation method thereof. The prosthetic valve leaflet material is made of polyurethane and includes an inner layer and surface layers located on opposite sides of the inner layer in the thickness direction, wherein the elastic modulus of the surface-layer polyurethane is greater than that of the inner-layer polyurethane. The valve leaflet material simultaneously takes into account fluid dynamics, biostability, biocompatibility, creep resistance, and fatigue resistance, achieving the performance required of the heart valves.Type: ApplicationFiled: December 25, 2025Publication date: April 30, 2026Inventors: Lichao Wang, Xing Wei, Dajun Kuang, Manman Zhao, Lingfeng Yang
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Patent number: 12598091Abstract: Disclosed are a consensus method and device, and a blockchain system. A primary node directly broadcasts a transaction hash list including a hash value of at least one unverified transaction in the system, so that a backup node and the primary node simultaneously verify the at least one unverified transaction, and the backup node stores a first verification result obtained by verification and a first hash value of the at least one unverified transaction. The primary node broadcasts an obtained second verification result and a second hash value of the at least one unverified transaction in a pre-preparation message after completing the verification, so that the backup node searches for the first verification result based on the second hash value, and broadcast a preparation message when the second verification result is the same as the searched first verification result, to enter a subsequent consensus stage, and complete the consensus processing.Type: GrantFiled: June 6, 2022Date of Patent: April 7, 2026Assignee: CHINA ACADEMY OF INFORMATION AND COMMUNICATIONS TECHNOLOGYInventors: Jian Jin, Jiagui Xie, Xufeng Ma, Jian Guo, Bo Zhang, Xing Wei
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Patent number: 12593626Abstract: In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 ?, respectively, so as to realize the flatness of the silicon-on-insulator film.Type: GrantFiled: April 24, 2023Date of Patent: March 31, 2026Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCESInventors: Xing Wei, Ziwen Wang, Rongwang Dai
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Publication number: 20260085450Abstract: The present invention provides a crystal growing apparatus and a RF-SOI substrate for growing a crystal. The crystal growing apparatus may comprise: a crucible, a first superconducting coil and a second superconducting coil, a controller and a pulling-up mechanism. The first superconducting coil and the second superconducting coil, distributed outside the crucible, are opposite to each other to generate a magnetic field in the crucible. The controller controls the first superconducting coil generating the first current and controlling the second superconducting coil generating the second current, wherein a value of the first current is not equal to a value of the second current. The pulling-up mechanism pulls up to grow a single crystal in the magnetic field in the crucible, which is asymmetric magnetic field, based on the first current and the second current.Type: ApplicationFiled: December 3, 2025Publication date: March 26, 2026Applicants: Zing Semiconductor Corporation, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of SciencesInventors: Xing WEI, Wenkai LIU, Zhongying XUE, Yun LIU, Rongwang DAI, Minghao LI, Yuehui YU
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Publication number: 20260053798Abstract: The present disclosure relates to combination therapies for treating a RAS related disease or disorder (e.g., cancer). In particular, the present disclosure relates to methods of treating a RAS related disease or disorder in a subject in need thereof, comprising administering to the subject a therapeutically effective amount of a RAS(ON) inhibitor in combination with one or more additional therapeutic agents, pharmaceutical compositions comprising a therapeutically effective amounts of the same, kits comprising the compositions and methods of use therefor.Type: ApplicationFiled: November 3, 2025Publication date: February 26, 2026Inventors: Ida ARONCHIK, Cristina BLAJ, Lingyan JIANG, Jingjing JIANG, Mark LABRECQUE, Bianca Jennifer LEE, Marie MENARD, Elsa QUINTANA, Kyle SEAMON, Lillian SEU, Mallika SINGH, Nataliya Tovbis SHIFRIN, Vidyasiri VEMULAPALLI, Yingyun WANG, Xing WEI, Caroline E. WELLER, David E. WILDES, Yu Chi YANG, Yongxian ZHUANG, David Church MONTGOMERY
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Publication number: 20260041823Abstract: The present disclosure discloses an implantable material, a synthesis method therefor, and a prosthetic heart valve. The implantable material is made of polyurethane, whose molecular chain structure includes soft and hard segments. Functional side chains are grafted onto the hard segment, and the functional side chains have a solubility parameter in a range of 6 to 8. In the present disclosure, the introduction of functional side chains into the hard segments enhances compatibility between the hard and soft segments while increasing stress transfer points between them. This results in implantable polymer material with superior mechanical properties.Type: ApplicationFiled: October 17, 2025Publication date: February 12, 2026Inventors: Lichao Wang, Xing Wei, Dajun Kuang
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Publication number: 20260028515Abstract: This disclosure relates to a one-part condensation curable silicone sealant composition suitable for use as a construction sealant for silicone structural glazing (SSG) applications, in particular for use in curtain wall façade systems. The one-part condensation curable silicone sealant composition contains an alkoxylated MQ silicone resin, optionally in the presence of a polysiloxane carrier fluid. When the one-part condensation curable silicone sealant composition is cured, the resulting sealant is designed to maintain adhesive integrity and to be stable in extreme climates, particularly at high temperatures.Type: ApplicationFiled: September 28, 2022Publication date: January 29, 2026Inventors: Zhiping ZENG, Yi GUO, Xing WEI, Xiuyan WANG, Jiang PENG
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Publication number: 20260023907Abstract: The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and/or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and/or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.Type: ApplicationFiled: August 19, 2024Publication date: January 22, 2026Inventors: Yu YE, Feng YUAN, Xing WEI, Yi DIAO, Xiaoqing YANG, Linhan ZHENG, Yibo WANG, Xiaoqiang LI
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Publication number: 20260018362Abstract: Disclosed is a method for manufacturing a field emitter, comprising: forming a primary epitaxial layer on a substrate; forming a plurality of secondary epitaxial structures on the primary epitaxial layer; forming an emitter electrode layer and a dielectric layer between the emitter electrode layer and the plurality of secondary epitaxial structures on the primary epitaxial layer; sequentially forming a protective layer, an insulating layer, a gate electrode layer and a planarization layer which are laminated on the dielectric layer and the plurality of secondary epitaxial structures; etching the planarization layer to expose part of the gate electrode layer on the dielectric layer and part of the secondary epitaxial structure; etching and removing the protective layer, the insulating layer and the exposed part of the gate electrode layer on part of the secondary epitaxial structure so as to expose part of the secondary epitaxial structure; forming a gate connection electrode layer on the exposed gate electrodType: ApplicationFiled: October 31, 2022Publication date: January 15, 2026Inventors: Wenchao Shen, Xiaodong Zhang, Xing Wei, Wenxin Tang, Jiaan Zhou, Baoshun Zhang
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Publication number: 20260005014Abstract: The present invention provides a method for sacrificed oxidation of a top silicon layer in a bonded wafer, including: providing the bonded wafer, which includes a substrate layer, the top silicon layer and an insulating buried oxide layer; and performing first and second furnace oxidation processes on the top silicon layer. A first oxide layer is formed on the surface of the top silicon layer, and a second oxide layer is formed on the surface of the top silicon layer as a result of the second furnace oxidation process. The first and second oxide layers have complementary thickness profiles on a top surface of the top silicon layer, and the first and second furnace oxidation processes are followed by respective wet etching processes for removing the first and second oxide layers. With the present invention, the top silicon layer can be thinned, and its thickness uniformity can be improved.Type: ApplicationFiled: June 27, 2025Publication date: January 1, 2026Inventors: Ziwen WANG, Wei ZHU, Yuhao ZHOU, Xing WEI, Wei LI
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Publication number: 20260005037Abstract: The present invention provides a method for reinforcing a bonded wafer, which includes: providing the bonded wafer, which includes a substrate layer, a top silicon layer and an insulating buried oxide layer; performing a first thermal reinforcing process on the bonded wafer; performing an edge grinding process on an unbonded region along the periphery of the top silicon layer; and performing a second thermal reinforcing process on the bonded wafer at a temperature higher than a temperature at which the first thermal reinforcing process is performed.Type: ApplicationFiled: June 27, 2025Publication date: January 1, 2026Inventors: Ziwen WANG, Wei ZHU, Xing WEI, Wei LI
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Publication number: 20250387224Abstract: Disclosed are a polymer valve leaflet material, a valve leaflet, a valve and a preparation method thereof. The polymer valve leaflet material is made of polyurethane and has a tensile strength in a range of 35 MPa to 60 MPa, an elastic modulus in a range of 15 MPa to 40 MPa, a softness in a range of 20° to 50°, and a thickness in a range of 0.10 mm to 0.20 mm.Type: ApplicationFiled: June 30, 2025Publication date: December 25, 2025Inventors: Lichao Wang, Xing Wei, Manman Zhao, Dajun Kuang, Yuting Zhu
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Publication number: 20250390653Abstract: The present invention provides an ECO method based on adaptive learning applied to ECO operations of netlists in different stages in a chip design process. The method comprises acquiring a first netlist subjected to an ECO in a previous stage and a second netlist to be subjected to an ECO in a current stage; determining a position where the ECO of the previous stage involves netlist modification based on a structural similarity between the first netlist and the second netlist, and delineating an input boundary and an output boundary in the first netlist; searching for, in the second netlist, matching signals matching the input boundary and output boundary delineated in the first netlist; delineating a boundary range of the second netlist to be subjected to the ECO based on the matching signals; and performing the ECO in the delineated boundary range. The method improves efficiency and accuracy of the ECO.Type: ApplicationFiled: July 22, 2024Publication date: December 25, 2025Inventors: Xiao ZHANG, Yi DIAO, Xing WEI, Feng YUAN, Xiaoqing YANG, Linhan ZHENG, Lin DING
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Publication number: 20250389003Abstract: A steel strip having excellent workability and corrosion resistance that requires no oil coating, and a manufacturing method therefor. The steel strip comprises a substrate and a phosphatization layer and a stearate lubricant layer provided on the substrate. The upper surface of the steel strip sequentially comprises, from inside to outside, the phosphatization layer and the stearate lubricant layer, with a surface roughness Ra in the range of 0.6 to 1.8 ?m and Rz in the range of 6 to 16 ?m, providing good surface lubricity during extension process. The lower surface of the steel strip has the stearate lubricant layer with a surface roughness Ra of 0.3 ?m or less and Rz of 2 ?m or less, offering good lubricity and high surface cleanliness.Type: ApplicationFiled: January 4, 2023Publication date: December 25, 2025Inventors: Yanliang Zhao, Xing Wei, Yigang Dai
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Patent number: 12474277Abstract: The present invention provides a method for determining the type of defects in a monocrystalline silicon wafer, which includes the steps of: using LST to measure particles in an as-grown silicon wafer and thereby obtaining a first measurement, and determining a V-rich region based on the first measurement and a first preset density value; and subjecting the silicon wafer to a thermal treatment, again using LST to measure particles in the silicon wafer and thereby obtaining a second measurement, and determining a Pv region, an I-rich region and a Pi region based on the second measurement, a second preset density value and a third preset density value. As a result, a particle density can be utilized as a basis for accurately and efficiently determining a region of interest of a monocrystalline silicon wafer as one of a V-rich region, a Pv region, a Pi region and an I-rich region.Type: GrantFiled: December 4, 2023Date of Patent: November 18, 2025Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Xing Wei, Hao Wang, Minghao Li, Yuehui Yu
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Patent number: 12468987Abstract: A computer-implemented system, platform, programing product, and/or method for improving transformation selection in an ensemble machine learning (ML) model that includes: providing all base ML models of the ensemble ML model; identifying all of a plurality of Derived Fields in all the base ML models; performing a Derived Field run prediction analysis for all the Derived Fields; computing the Derived Field Importance Weight for Field (DFIW4F) and the Derived Field Importance Weight for Model (DFIW4M) for all the Derived Fields; clustering all the Derived Fields into a plurality of Derived Field clusters, wherein each Derived Field cluster is based upon the DFIW4M and the DFIW4F for the Derived Field; sorting all the Derived Field clusters by best cluster based upon DFIW4M and DFIW4F; and running the base ML models based upon the Derived Fields in the best Derived Field cluster until sufficient base ML models have been run.Type: GrantFiled: May 9, 2022Date of Patent: November 11, 2025Assignee: International Business Machines CorporationInventors: Dong Hai Yu, Jun Wang, Bo Song, Yao Dong Liu, Jiang Bo Kang, Lei Tian, Xing Wei
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Publication number: 20250328713Abstract: The present application provides a method for obtaining an engineering change order (ECO) point based on a comparison of design files, for finding difference ECO points between a revision design and an original design in a chip design, the method includes finding an old GTECH file corresponding to the original design and a new GTECH file corresponding to the revision design; comparing the old GTECH file and the new GTECH file to find key point information; and based on the key point information, analyzing a component composition and connection of a circuit, to find the difference ECO points.Type: ApplicationFiled: May 9, 2024Publication date: October 23, 2025Inventors: Xiao ZHANG, Xing WEI, Feng YUAN, Yi DIAO, Tak-Kei LAM, Xiaoqing YANG
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Patent number: 12400917Abstract: The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm?cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.Type: GrantFiled: November 30, 2021Date of Patent: August 26, 2025Assignees: Zing Semiconductor Corporation, SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCESInventors: Xing Wei, Minghao Li, Zhongying Xue
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Patent number: 12398485Abstract: The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects.Type: GrantFiled: April 15, 2022Date of Patent: August 26, 2025Assignees: Zing Semiconductor Corporation, SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCESInventors: Xing Wei, Yun Liu, Xun Wang, Zhongying Xue