Abstract: In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 ?, respectively, so as to realize the flatness of the silicon-on-insulator film.

Abstract: The present invention relates to a preparation method of a P-type high-resistance and ultra-high-resistance Czochralski monocrystalline silicon substrate. According to the present invention, an oxygen concentration in a silicon wafer is controlled to match with a resistivity, so as to realize that a conductive type of the silicon substrate does not change after a device is manufactured, and that the silicon substrate has a high resistivity. The oxygen concentration and the resistivity in silicon crystal can be adjusted separately or together; and operation is flexible, and a yield of a high-resistance silicon crystal is greatly improved.

Abstract: A main and auxiliary alloy-based neodymium-iron-boron magnet material and the preparation method thereof. The raw material composition for the main and auxiliary alloy-based neodymium-iron-boron magnet material includes a main alloy raw material and an auxiliary alloy raw material, wherein the mass percentage of the auxiliary alloy raw material in the raw material composition for the main and auxiliary alloy-based neodymium-iron-boron magnet material is 1.0-15.0 mass %. For the main and auxiliary alloy-based neodymium-iron-boron magnet material prepared by using the raw material composition, the coercivity is increased while high remanence is ensured, and the preparation method therefor can be suitable for engineering applications.

Abstract: A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 ?, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Abstract: A system is described for redirecting multimedia in a collaborative session on a virtual desktop. The virtual desktop session can be established, and collaborator virtual desktop clients can be connected in a collaborative session where each collaborator can view the desktop GUI in their respective virtual desktop client. A request can be received to play media in a media player in the virtual desktop. The media stream can be intercepted in the virtual desktop before it is rendered in the media player and conveyed to each collaborator's client over a separate virtual channel established between the virtual desktop and each collaborator. The data stream can then be rendered in a client media player by each collaborator's client.

Abstract: A computer-implemented system, platform, programing product, and/or method for improving transformation selection in an ensemble machine learning (ML) model that includes: providing all base ML models of the ensemble ML model; identifying all of a plurality of Derived Fields in all the base ML models; performing a Derived Field run prediction analysis for all the Derived Fields; computing the Derived Field Importance Weight for Field (DFIW4F) and the Derived Field Importance Weight for Model (DFIW4M) for all the Derived Fields; clustering all the Derived Fields into a plurality of Derived Field clusters, wherein each Derived Field cluster is based upon the DFIW4M and the DFIW4F for the Derived Field; sorting all the Derived Field clusters by best cluster based upon DFIW4M and DFIW4F; and running the base ML models based upon the Derived Fields in the best Derived Field cluster until sufficient base ML models have been run.

Abstract: A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

Abstract: A biological material is provided and prepared by performing (a) oxidation, (b) first cross-linking, (c) second cross-linking, and (d) dehydration on a biological material for preparation; wherein (b) is performed after (a), and (a), (b), and (c) are all performed prior to (d); during oxidation, an oxidizing agent able to cause hydroxy groups to be converted to aldehyde groups is utilized, the hydroxy groups coming from mucopolysaccharides in the biological material; during first cross-linking, a first cross-linking agent able to cause cross-linking between aldehyde groups of mucopolysaccharides is utilized; and during second cross-linking, a second cross-linking agent able to cause cross-linking between collagen fibers in the biological material is utilized.

Abstract: In an approach to improve video searching embodiments execute heuristic video searching based on importance of semantic features. Embodiments perform hierarchical aggregation of a parsed video into one or more clusters of video excerpts based on a plurality of video features, and display a word cloud to a user to guide feedback. Embodiments traverse the one or more clusters based on a data structure of the hierarchical aggregation and the feedback. Additionally, responsive to reaching selected leaf nodes of the data structure, embodiments generate one or more snapshots of the video excerpts associated with the leaf nodes, wherein the leaf nodes are selected based on the feedback. Further, embodiments display the one or more generated snapshots of the video excerpts to the user.

Abstract: The present invention provides a method of growing a single-crystal silicon, comprising: loading a batch of polysilicon material in a crucible of a furnace, heating the crucible to melt the polysilicon material into a mass of silicon melt, confirming a liquid surface of the mass of silicon melt, applying a superconducting magnetic field to the mass of silicon melt with a magnetic field generator and adjusting a position of the magnetic field generator to position a maximum point of the superconducting magnetic field within a predetermined range under the liquid surface, and dipping a seed crystal into the silicon melt, and pulling the seed crystal during rotation of the seed crystal to crystallize the single crystal under the seed crystal until forming an ingot of single-crystal silicon. Oxygen content in the ingot is controlled through positioning the maximum point of the superconducting magnetic field under the liquid surface.

Abstract: A set of classifiable data containing a plurality of classes is ingested. A target class within the plurality of classes is determined. Using the set of classifiable data, an interactive recall rate chart is generated, and the interactive recall rate chart shows a set of target class recall rates against a set of class recall rates for the remainder of the plurality of classes. The interactive recall rate chart is presented to a user. A target class recall rate selection from the set of target class recall rates is received from the user. The set of classifiable data is reclassified, based on the target class recall rate selection.

Abstract: A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

Abstract: The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

Abstract: A computer implemented method for managing datasets for a histogram. The method uses a number of processor units to determine a first span for first bins containing first datapoints in a first dataset in the datasets. The first span is determined based a distribution of the first datapoints in the first dataset and a desired number of bins. The number of processor units adjusts a second span for second bins containing second datapoints in a second dataset in the datasets to form an adjusted span that matches the first span for the first bins. The number of processor units merges the first datapoints in the first bins having the first span with the second datapoints in the second bins having the adjusted span to form a merged dataset for the histogram.

Abstract: A register-transfer level signal mapping construction method and device, wherein the register-transfer level signal mapping construction method comprises: acquiring register-transfer level codes and netlist level codes corresponding to the register-transfer level codes; constructing a circuit according to the register-transfer level codes and the netlist level codes; separating the circuit into a plurality of modules according to syntax of the circuit in a hardware description language; determining a correspondence relationship between the plurality of modules with logic verification methods; acquiring register-transfer level signals of a mapping relationship to be established; and determining netlist level signals corresponding to the register-transfer level codes according to the correspondence relationship between the plurality of modules.

Abstract: A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Abstract: Embodiments of the present disclosure relate to methods, systems, and computer program products for optimized prediction of a tree ensemble. According to a method, an input request is received, which indicates a plurality of input values for a plurality of variables associated with a tree ensemble. A plurality of target transformed intervals, into which the plurality of input values fall respectively, are determined by matching the plurality of input values with a plurality of sets of transformed intervals for the plurality of variables respectively. Respective prediction results for a plurality of tree models of the tree ensemble are determined based on the plurality of target transformed intervals and respective node hierarchies of the plurality of tree models. A tree ensemble prediction result is determined for the input request based on the determined prediction results of the plurality of tree models.

Abstract: The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon.

Abstract: The present disclosure relates to a method for treating a wafer surface. By controlling the gas composition at each stage of the treatment process, and corresponding processes of heating and annealing, and cooling and thinning by oxidation, the final wafer is enabled to have a surface roughness of less than 5 ?. This effectively reduces the cost of the final treatment process and has good application prospects.

Abstract: A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.