Abstract: The present disclosure relates to an OLED display panel. The OLED display panel includes a TFT array substrate, and a flat layer on the TFT array substrate. The flat layer includes a first flat layer and a second flat layer on the first flat layer. A viscosity of the first flat layer is less than a viscosity of the second flat layer. In addition, the present disclosure also relates to a manufacturing method of the OLED display panel to enhance the performance of the OLED display panel.

Abstract: A pixel circuit, a driving method and a display, comprising: a compensation circuit (1) being electrically connected to a driving circuit (2) via a first node (N1); an external power supply (ELVDD), the driving circuit (2) and a light-emitting diode (EL4) being connected in series; a capacitor (C3) being located between the first node (N1) and the external power supply (ELVDD), wherein the compensation circuit (1) is used for setting the voltage of the first node (N1) to a first voltage (Vdata+VthT1) by means of a compensation transistor; the capacitor (C3) is used for maintaining the voltage of the first node (N1) as the first voltage (Vdata+VthT1); the driving circuit (2) externally connects a first control signal (En) to generate a driving current (IEL4) to drive the light-emitting diode (EL4) to emit light; and a driving transistor in the driving circuit (2) and the compensation transistor are common-gate transistors.

Abstract: The present disclosure provides a pixel circuit, a driving method, pixel structure and display panel. A driving unit of the pixel circuit includes an isolating transistor, driving transistor and light emitting control transistor coupled between an external power supply and light emitting unit in series with source and drain electrodes. Both gates of the light emitting control transistor and isolating transistor receive a first control signal, and the driving transistor and compensating transistor are transistors with common gate region. The driving transistor is used to generate a driving current to drive the light emitting unit to emit light when the isolating transistor and light emitting control transistor are turned on under the control of the first control signal, and the driving current is obtained according to the first voltage, a voltage of the external power supply, and a threshold voltage of the driving transistor in the driving unit.

Abstract: The present disclosure discloses a pixel circuit, a driving method and a display, including: a compensation unit connected with a driving unit; an external power supply, a driving unit and a first light emitting unit sequentially connected in series; a capacitor disposed between a first node and the external power supply; and an initialization unit with a first initialization transistor having a first electrode of connected to the first node, a gate electrode externally connected to a second scan signal, and a second electrode connected to a second light emitting unit, and a second initialization transistor having a first electrode connected to the second light emitting unit, a second electrode connected to an initialization voltage and a gate electrode externally connected to a second scan signal. The first initialization transistor and the second initialization transistor are a dual-gate transistor.

Abstract: A pixel circuit, a driving method and a display device having the pixel circuit are disclosed, wherein the pixel circuit comprises a compensation unit, a driving unit, a light emitting unit, a capacitor, an initialization unit and an external power supply and the driving method comprises a first initialization stage, a second initialization stage, a data writing stage and a light emitting stage.

Abstract: A pixel circuit, a driving method and a display, comprising: a compensation circuit (1) being electrically connected to a driving circuit (2) via a first node (N1); an external power supply (ELVDD), the driving circuit (2) and a light-emitting diode (EL4) being connected in series; a capacitor (C3) being located between the first node (N1) and the external power supply (ELVDD), wherein the compensation circuit (1) is used for setting the voltage of the first node (N1) to a first voltage (Vdata+VthT1) by means of a compensation transistor; the capacitor (C3) is used for maintaining the voltage of the first node (N1) as the first voltage (Vdata+VthT1); the driving circuit (2) externally connects a first control signal (En) to generate a driving current (IEL4) to drive the light-emitting diode (EL4) to emit light; and a driving transistor in the driving circuit (2) and the compensation transistor are common-gate transistors.

Abstract: The present disclosure discloses a method of manufacturing a thin film transistor (TFT) array substrate including a step of preparing a patterned active layer on a base substrate, wherein the step includes: sequentially forming an amorphous silicon (a-Si) thin film layer and a boron-doped (B-doped) amorphous silicon germanium (a-SiGe) thin film layer on the base substrate; performing crystallization on the a-Si thin film layer and the B-doped a-SiGe thin film layer using a thermal annealing process to obtain a polycrystalline silicon (poly-Si) thin film layer and a B-doped polycrystalline silicon germanium (poly-SiGe) thin film layer; and forming the patterned active layer by using a photolithography process to etch the poly-Si thin film layer and the B-doped poly-SiGe thin film layer. The present disclosure further discloses a TFT array substrate and a display device including the TFT array substrate.

Abstract: The present invention provides a CMOS inverter and array substrate. The CMOS inverter comprises a P-type low-temperature polysilicon thin film transistor electrically coupled to a N-type metal-oxide thin film transistor; the P-type low-temperature polysilicon thin film transistor and the N-type metal-oxide thin film transistor satisfy the relationship: C n ? W n L n ? ? n = C P ? W P L P ? ? P ; wherein, Cn and CP is a gate-insulating-layer capacitance of the N-type metal oxide TFT and the P-type low-temperature polysilicon TFT, respectively, W n L n ? ? and ? ? W P L P is a channel width-length ratio of the N-type metal-oxide TFT and the P-type low-temperature polysilicon TFT, respectively, ?n and ?P is a mobility of the N-type metal-oxide TFT and P-type low-temperature polysilicon TFT. The performance of the CMOS inverter could be improved and the manufacturing complexity and cost of the CMOS could be reduced.

Abstract: The present disclosure discloses a thin film transistor array substrate including an active layer disposed on a base substrate, wherein the active layer includes a first active region and a second active region located in a same structural layer, the first active region has a material comprising poly-silicon, and includes a first channel region, and a first source region and a first drain region that are located at both sides of the first channel region, respectively, the first source region having a first contact layer disposed thereon, the first drain region having a second contact layer disposed thereon, and materials of both the first and second contact layers being boron-doped poly-silicon; and the second active region has a material comprising metal oxide semiconductor, and includes a second channel region and a second source region and a second drain region that are located at both sides of the second channel region, respectively.

Abstract: A manufacturing method for a thin-film transistor array substrate is disclosed. The method includes: providing a base substrate; depositing a first metal layer on the base substrate, and patterning to form a gate electrode and a first storage electrode; depositing a gate insulation layer, wherein the gate insulation layer covers the gate electrode and the first storage electrode; depositing a metal oxide semiconductor layer, and patterning to form a metal oxide active layer; depositing a second insulation layer, and patterning to form an etching barrier layer; depositing a second metal layer, and pattering to form a source electrode, a drain electrode and a second storage electrode, wherein the first storage electrode and the second storage electrode are two electrodes of a storage capacitor; depositing a third insulation layer, and patterning to form a passivation layer; and depositing a third metal layer, and patterning to form a pixel electrode.

Abstract: The disclosure provides a back-channel-etch type oxide semiconductor TFT substrate and fabricating method thereof. The method configures an active layer as a double layer structure, and a first oxide semiconductor layer located in a lower layer is prepared according to normal deposition process parameters and has normal density and a second oxide semiconductor layer located in an upper layer is prepared by changing deposition process parameters and has higher density; the first oxide semiconductor layer has lower density and higher mobility and the second oxide semiconductor layer has higher density, fewer numbers of film defects, more strong etch resistance, it is capable of reducing damage of a channel region of an active layer during the process for etching a drain electrode and a source electrode, and at the same time saves a mask for a etch stop layer, cuts down the fabricating cost.

Abstract: The present disclosure discloses a method of manufacturing a thin film transistor (TFT) array substrate including a step of preparing a patterned active layer on a base substrate, wherein the step includes: sequentially forming an amorphous silicon (a-Si) thin film layer and a boron-doped (B-doped) amorphous silicon germanium (a-SiGe) thin film layer on the base substrate; performing crystallization on the a-Si thin film layer and the B-doped a-SiGe thin film layer using a thermal annealing process to obtain a polycrystalline silicon (poly-Si) thin film layer and a B-doped polycrystalline silicon germanium (poly-SiGe) thin film layer; and forming the patterned active layer by using a photolithography process to etch the poly-Si thin film layer and the B-doped poly-SiGe thin film layer. The present disclosure further discloses a TFT array substrate and a display device including the TFT array substrate.

Abstract: The present disclosure provides a top-gate self-aligned metal oxide semiconductor TFT and a manufacturing method thereof. By providing a light-shielding layer below an active layer to protect the active layer from light irradiation and prevent the TFT from generating a negative threshold voltage drift phenomenon. Further, by connecting the light-shielding layer to the source, a stable voltage is generated on the light-shielding layer to avoid the floating gate effect, so as to improve the working stability of the TFT effectively. The top-gate self-aligned metal oxide semiconductor TFT produced by the method of the present disclosure does not generate negative threshold voltage drift phenomenon and floating gate effect, resulting in good working stability.

Abstract: The present disclosure provides an organic light-emitting diode (OLED) display panel including an array substrate and a color filter cover plate. The array substrate includes a thin film transistor layer and an OLED layer. The color filter cover plate includes a color resist layer. The color resist layer includes a first color resist region and a second color resist region. The first color resist region corresponds to the OLED layer, and the second color resist region corresponds to the thin film transistor layer. The second color resist region includes two or three color resist blocks that are stacked on each other and have different colors.

Abstract: A manufacturing method for a thin-film transistor array substrate is disclosed. The method includes: providing a base substrate; depositing a first metal layer on the base substrate, and patterning to form a gate electrode and a first storage electrode; depositing a gate insulation layer, wherein the gate insulation layer covers the gate electrode and the first storage electrode; depositing a metal oxide semiconductor layer, and patterning to form a metal oxide active layer; depositing a second insulation layer, and patterning to form an etching barrier layer; depositing a second metal layer, and pattering to form a source electrode, a drain electrode and a second storage electrode, wherein the first storage electrode and the second storage electrode are two electrodes of a storage capacitor; depositing a third insulation layer, and patterning to form a passivation layer; and depositing a third metal layer, and patterning to form a pixel electrode.

Abstract: The present disclosure provides a pixel circuit, a driving method, pixel structure and display panel. A driving unit of the pixel circuit includes an isolating transistor, driving transistor and light emitting control transistor coupled between an external power supply and light emitting unit in series with source and drain electrodes. Both gates of the light emitting control transistor and isolating transistor receive a first control signal, and the driving transistor and compensating transistor are transistors with common gate region. The driving transistor is used to generate a driving current to drive the light emitting unit to emit light when the isolating transistor and light emitting control transistor are turned on under the control of the first control signal, and the driving current is obtained according to the first voltage, a voltage of the external power supply, and a threshold voltage of the driving transistor in the driving unit.

Abstract: The present application discloses a method for fabricating a TFT backplane and a TFT backplane. The method includes: providing a substrate; subsequently forming a first active region, a first oxide layer, a nitride layer and a first and a second gate independently of each other on the substrate; removing the nitride layer not covered by the first and second gate electrodes; depositing a second insulating layer; forming a second active region with different material from the first active region on the on the second insulating layer above the second gate electrode; forming a first and a second source electrodes, a first and a second drain electrodes respectively. This method can improve the performance of the TFT backplane.

Abstract: The present disclosure provides a top-gate self-aligned metal oxide semiconductor TFT and a manufacturing method thereof. By providing a light-shielding layer below an active layer to protect the active layer from light irradiation and prevent the TFT from generating a negative threshold voltage drift phenomenon. Further, by connecting the light-shielding layer to the source, a stable voltage is generated on the light-shielding layer to avoid the floating gate effect, so as to improve the working stability of the TFT effectively. The top-gate self-aligned metal oxide semiconductor TFT produced by the method of the present disclosure does not generate negative threshold voltage drift phenomenon and floating gate effect, resulting in good working stability.

Abstract: The present disclosure relates to an array substrate, a display device, and the manufacturing method thereof. The array substrate includes a substrate, and a first gate electrode layer, a first insulation layer, a trench layer, a source/drain electrode layer, a second insulation layer, a pixel electrode layer and a second gate electrode layer formed on the substrate in sequence. The pixel electrode layer and the second gate electrode layer are spaced apart from each other. The second gate electrode layer, the first gate electrode layer, and the source/drain electrode layer form at least one thin film transistor (TFT) having a dual-gate structure. With such configuration, the driving forces of the array substrate may be greatly enhanced.

Abstract: The present invention discloses an organic light-emitting diode display device and a driving method thereof. The device includes: a plurality of pixels, including a plurality of organic light-emitting diodes and a plurality of drive transistors for supplying drive currents to the organic light-emitting diodes; a data driver, configured to transmit corresponding data signals to the plurality of pixels via a plurality of data lines; and a pre-charge circuit, configured to pre-charge voltage signals reserved in a previous time sequence to an initial voltage, the initial voltage being less than or equal to a minimum voltage of the data signals, wherein before the data driver transmits the corresponding data signals to the plurality of pixels, the pre-charge circuit acts to pre-charge the voltage signals reserved in the previous time sequence by the plurality of pixels to be less than or equal to the minimum voltage of the data signals.