Patents by Inventor Xinhui Wang

Xinhui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110171788
    Abstract: A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.
    Type: Application
    Filed: January 11, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang, Haizhou Yin
  • Patent number: 7955928
    Abstract: A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang
  • Publication number: 20110108918
    Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Haizhou Yin, Xinhui Wang, Kevin K. Chan, Zhibin Ren
  • Publication number: 20110079855
    Abstract: FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. CHAN, Zhibin REN, Xinhui WANG, Keith Kwong Hon WONG
  • Publication number: 20110062518
    Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
  • Publication number: 20110049630
    Abstract: A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each FET includes a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a source stressor, and a drain stressor disposed across from the source stressor relative to the gate electrode, wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Applicant: International Business Machines Corporation
    Inventors: Amlan Majumdar, Xinhui Wang
  • Patent number: 7887822
    Abstract: Provided in the present invention are recombinant peptides and a method for using the peptides in stimulating an immune response against human high molecular weight-melanoma associated antigen (HMW-MAA). The peptides were designed from the identification of regions of structural and amino acid sequence homology between HMW-MAA and the mouse anti-idiotypic monoclonal antibody MK2-23. The method comprises the step of administering to an individual a peptide of the invention in an amount effective to elicit an immune response against HMW-MAA.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: February 15, 2011
    Assignees: Health Research, Inc., Hauptman-Woodward Medical Research Institute
    Inventors: Soldano Ferrone, Chien-Chung Chang, Wei Luo, Xinhui Wang, Debashis Ghosh
  • Publication number: 20110027948
    Abstract: A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhibin Ren, Xinhui Wang, Kevin K. Chan, Ying Zhang
  • Patent number: 7872303
    Abstract: At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Qiqing Christine Ouyang, Dae-Gyu Park, Xinhui Wang
  • Publication number: 20100244103
    Abstract: A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang
  • Publication number: 20100105187
    Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
    Type: Application
    Filed: January 6, 2010
    Publication date: April 29, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhibin Ren, Ghavam Shahidi, Dinkar V. Singh, Jeffrey W. Sleight, Xinhui Wang
  • Patent number: 7682913
    Abstract: A process for making a MCSFET includes providing a first implant through a first side of an elongated stack, and then providing a second implant through a second side of the stack. The first implant has a dose different than the dose of the second implant, so that final dopant concentrations in the first and second sides differ and the transistor has two threshold voltages Vt1, Vt2.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Xu Ouyang, Louis Lu-Chen Hsu, Xinhui Wang, Haizhou Yin
  • Publication number: 20100038679
    Abstract: At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Applicant: International Business Machines Corporation
    Inventors: KEVIN K. CHAN, Qiqing (Christine) Ouyang, Dae-Gyu Park, Xinhui Wang
  • Patent number: 7659583
    Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Zhibin Ren, Ghavam Shahidi, Dinkar V. Singh, Jeffrey W. Sleight, Xinhui Wang
  • Patent number: 7592421
    Abstract: The present invention provides peptide mimics for HLA class II antigens. The peptide mimics were identified by panning phage display peptide libraries with anti-HLA class II monoclonal antibodies. The peptide mimics inhibit the binding of an anti-HLA class II antigen antibody to HLA class II antigen positive cells and also elicit antibodies which can bind to HLA class II antigen positive cells. The identified peptide mimics can be used as immunogens for therapy of diseases related to cells expressing the HLA class II antigen, such as Non-Hodgkins Lymphoma.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: September 22, 2009
    Assignee: Health Research, Inc.
    Inventors: Soldano Ferrone, Wei Luo, Xinhui Wang
  • Publication number: 20090045462
    Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhibin Ren, Ghavam Shahidi, Dinkar V. Singh, Jeffrey W. Sleight, Xinhui Wang
  • Publication number: 20070297983
    Abstract: Disclosed is a method for inhibiting the growth of breast carcinoma stem cells. that express High Molecular Weight -Melanoma Associated Antigen (HMW-MAA). The method comprises administering to an individual a composition comprising an antibody reactive with HMW-MAA or a fragment of such an antibody in an amount effective to inhibit the growth of the breast carcinoma cells. Also provided are methods for inhibiting metastasis of breast carcinomas and methods for identifying HMW-MAA+ breast cancer stem cells.
    Type: Application
    Filed: March 16, 2007
    Publication date: December 27, 2007
    Inventors: Soldano Ferrone, Xinhui Wang, Tim Clay, Kim Lyerly, Michael Morse, Gay Devi, Takuya Osada
  • Patent number: 7312524
    Abstract: A method for fabricating a thermally stable ultralow dielectric constant film including Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: December 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Alfred Grill, David R. Medeiros, Deborah Newmayer, Son Van Nguyen, Vishnubhai V. Patel, Xinhui Wang
  • Publication number: 20070190061
    Abstract: Provided in the present invention are recombinant peptides and a method for using the peptides in stimulating an immune response against human high molecular weight-melanoma associated antigen (HMW-MAA). The peptides were designed from the identification of regions of structural and amino acid sequence homology between HMW-MAA and the mouse anti-idiotypic monoclonal antibody MK2-23. The method comprises the step of administering to an individual a peptide of the invention in an amount effective to elicit an immune response against HMW-MAA.
    Type: Application
    Filed: July 17, 2006
    Publication date: August 16, 2007
    Inventors: Soldano Ferrone, Chien-Chung Chang, Wei Luo, Xinhui Wang, Debashis Ghosh
  • Publication number: 20060110937
    Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.
    Type: Application
    Filed: January 3, 2006
    Publication date: May 25, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINE CORPORATION
    Inventors: Stephen Gates, Alfred Grill, David Medeiros, Deborah Newmayer, Son Nguyen, Vishnubhai Patel, Xinhui Wang