Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

Abstract: FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

Abstract: A dual epitaxial integration process for FinFET devices. First and second pluralities of fins and gates are formed, with some of the fins and gates being for NFETs and some of the fins and gates being for PFETs. A first layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide is deposited over the NFETs and PFETs. The hard mask material is removed from one of the NFETs and PFETs and a first source and drain material is epitaxially deposited on the fins. A second layer of the hard mask material is deposited over the NFETs and PFETs. The first and second layers of the hard mask material are removed from the other of the NFETs and PFETs and a second source and drain material is deposited on the fins.

Abstract: A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w).

Abstract: A dual epitaxial integration process for FinFET devices. First and second pluralities of fins and gates are formed, with some of the fins and gates being for NFETs and some of the fins and gates being for PFETs. A first layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide is deposited over the NFETs and PFETs. The hard mask material is removed from one of the NFETs and PFETs and a first source and drain material is epitaxially deposited on the fins. A second layer of the hard mask material is deposited over the NFETs and PFETs. The first and second layers of the hard mask material are removed from the other of the NFETs and PFETs and a second source and drain material is deposited on the fins.

Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Abstract: Combinations of agents that have a synergistic effect for the treatment of a tumor are disclosed herein. These combinations of agents can be used to treat tumors, wherein the cells of the cancer express a mutated BRAF. Methods are disclosed for treating a subject diagnosed with a tumor that expresses a mutated BRAF. The methods include administering to the subject (1) a therapeutically effective amount of an antibody or antigen binding fragment thereof that specifically binds glucose regulated protein (GRP) 94; and (2) a therapeutically effective amount of a BRAF inhibitor. In some embodiments, the tumor is melanoma. In some embodiments the method includes selecting a subject with primary or secondary resistance to a BRAF inhibitor. In further embodiments, treating the tumor comprises decreasing the metastasis of the tumor. In additional embodiments, the BRAF inhibitor comprises PLX4032 or PLX4720.

Abstract: Combinations of agents that have a synergistic effect for the treatment of a tumor are disclosed herein. These combinations of agents can be used to treat tumors, wherein the cells of the cancer express a mutated BRAF. Methods are disclosed for treating a subject diagnosed with a tumor that expresses a mutated BRAF. The methods include administering to the subject (1) a therapeutically effective amount of an antibody or antigen binding fragment thereof that specifically binds glucose regulated protein (GRP) 94; and (2) a therapeutically effective amount of a BRAF inhibitor. In some embodiments, the tumor is melanoma. In some embodiments the method includes selecting a subject with primary or secondary resistance to a BRAF inhibitor. In further embodiments, treating the tumor comprises decreasing the metastasis of the tumor. In additional embodiments, the BRAF inhibitor comprises PLX4032 or PLX4720.

Abstract: A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

Abstract: A method for implementing a handover in a local switch, and the method comprises: when one party Mobile Station of a call implementing a local switch mode performs a Base Station Subsystem handover, the Base Station Subsystem handover transmits uplink speech data of the Mobile Station which does not need to perform the handover on a local switch link of the Base Station Subsystem and a link between the Base Station Subsystem and a Media Gateway simultaneously. A Base Station Subsystem implementing a handover in a local switch is also provided by the present invention.

Abstract: A method for indicating a frame mapping way is provided, including: a network side notifying a mobile station of information of a SACCH frame mapping way used by the mobile station. An apparatus for indicating a frame mapping way is further provided, including a determination unit and a notification unit, wherein the determination unit is for determining a used SACCH frame mapping way for a mobile station; the notification unit is for notifying the mobile station of information of a SACCH frame mapping way used by the mobile station. With the invention, the network side can notify the mobile station of the information of which frame mapping way is used determined for the mobile station, thereby solving the problem that the mobile station does not know which frame mapping way is used, greatly improving the performance of the communication system after the mobile station uses the determined frame mapping way.

Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

Abstract: The present invention discloses a method for implementing a handover in a local switch, and the method includes: a core network transmitting indication information to a source base station subsystem during any terminal of communication parties which carries out a local switch is performing a base station subsystem handover, and the source base station subsystem determining whether to transmit user-plane speech data received from a media gateway to the terminal which has not performed the base station subsystem handover, or to transmit the user-plane speech data received from an internal link to the terminal which has not performed the base station subsystem handover, according to the indication information. The present invention also discloses a system for implementing a handover in a local switch as well as a base station subsystem.

Abstract: A method for acquiring support capability of a mobile terminal by a base station side system is disclosed in the present disclosure, and the method includes: the base station side system applies a co-frequency interference to the mobile terminal, and detects a measurement report which is fed back by the mobile terminal after the co-frequency interference is applied, and determines and acquires the support capability of the mobile terminal for voice services over adaptive multi-user channels on one slot according to associated parameters in the detected measurement report in combination with associated threshold values. A system for acquiring support capability of the mobile terminal by the base station side system is also disclosed in the present disclosure.

Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.