Abstract: Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Abstract: A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

Abstract: A method of forming a semiconductor device includes forming a trench in a passivating layer between neighboring fins. A barrier is formed in the trench. Conductive contacts are formed in the passivating layer to provide electrical connectivity to the fins. The conductive contacts are in direct contact with sidewalls of the barrier. A semiconductor device includes a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract: A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.

Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Abstract: An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material.

Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.