Xuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: Disclosed is a crop yield prediction method and device. The method includes: transmitting an image acquisition instruction to a preset aircraft terminal to acquire a ground image; transmitting a driving instruction at the same time, wherein a distance between a first rail vehicle and a second rail vehicle is inversely proportional to the driving time, a plurality of light channels are embedded between a first rail and a second rail, and a light transmittance of the light channels is able to be affected by the external environment to change; transmitting a light emitting instruction and recording initial data when multiple beams of light are emitted; transmitting a light receiving instruction and recording final data when the multiple beams of light are received; and inputting the ground image, the initial data and the final data into a crop yield prediction model for processing.
Abstract: A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature.
Abstract: This invention relates to a thermally conductive potting composition, comprising a first part comprising at least one epoxy resin; at least one thermally conductive filler; and at least one metal complex; and a second part comprising at least one curing agent. The first part of the thermally conductive potting composition exhibits high thixotropic index and therefore the first part is easily stored. After the first part and the second part is mixed, the thermally conductive potting composition exhibits low thixotropic index and the meets the requirement for potting process.
Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.
Abstract: A method for manufacturing an IGBT device includes: forming a cell structure of the IGBT device in a substrate; forming front metal layers on the substrate; thinning the substrate; forming a collector region on the back of the substrate; forming back metal layers on the back of the substrate; and forming target metal on the front and back of the substrate via electroless plating processes.
Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.
Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.
Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.
Abstract: A method and apparatus for adjusting channelization of a traffic intersection are proposed. The specific implementation of the method is: obtaining a first traffic characteristic of vehicles at each of a plurality of target positions in a process of vehicles in a target traveling direction traveling through the traffic intersection from upstream to downstream in a preset first time period; generating first traffic change information of the traffic intersection based on the first traffic characteristic at each of the plurality of target positions; and in response to that the first traffic change information satisfies a preset first change distribution, generating channelization adjustment information for non-motorized vehicle lanes of the traffic intersection.
December 8, 2020
November 18, 2021
Qiqi XU, Fan YANG, Yongyi SUN, Chengfa WANG, Xuan HUANG
Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.
Abstract: The present invention provides a transceiver. The transistor is coupled to a transmission line. The transceiver includes a variable resistor set, a transmitter module, a receiver module, and a digital signal processor. The transmitter module has an output terminal coupled to the variable resistor set and the transmission line. The transmitter module includes a first digital-to-analog converter configured to output an emission current. The receiver module has an input terminal coupled to the transmitter module and the transmission line. When the emission current is fed into the transmission line, a far-end echo is fed into the receiver module. An amplitude of the far-end echo is associated with a resistance value of the transmission line. The digital signal processor adjusts a current value of the emission current from a first default current value to a second default current value based on the amplitude of the far-end echo.
Abstract: A semiconductor arrangement includes a well region, a transistor over the well region, a conductive line in conductive contact with a first source/drain region of the transistor and having a sidewall in conductive contact with a sidewall of the well region, and a liner layer disposed between the sidewall of the conductive line and the sidewall of the well region. A method includes forming a well region in a semiconductor layer. A first fin and a second fin are formed over the well region. A first spacer is formed on the first fin and a second spacer is formed on the second fin. A portion of the well region positioned between the first spacer and the second spacer is removed to define a trench. A liner layer is formed in the trench, and a conductive line is formed in the trench over the liner layer. The conductive line conductively contacts the well region.
November 26, 2019
Date of Patent:
November 9, 2021
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.
Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.
Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.
Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.
Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.
Abstract: A timing control method and a timing control apparatus for a signal light, and a storage medium are disclosed. The method includes: determining an optimal passing-through duration of a signal light corresponding to each passing-through direction at a target intersection according to traffic in the passing-through direction; determining a range of values for each variable in a calibration function corresponding to the target intersection according to a constraint to each passing-through direction at the target intersection, wherein the calibration function comprises the optimal passing-through duration corresponding to each passing-through direction and a variable corresponding to a final passing-through duration in each passing-through direction; and calculating the final passing-through duration in each passing-through direction in a case where the calibration function meets a preset condition, according to the range of values for each variable.
September 29, 2020
Date of Patent:
October 5, 2021
BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
Xuan Huang, Fan Yang, Hui Yuan, Yongyi Sun, Chengfa Wang, Qiqi Xu