Abstract: A method, computer program product and system are provided for preloading debug information based on the presence of incremental source code files. Based on parsed input parameters to a source code debugger, a source code repository and a local storage area are searched for an incremental file. In response to the incremental file being located, a preload indicator in the incremental file, which is a source code file, is set. Based on the preload indicator being set, debug symbol data from the incremental file is merged to a preload symbol list. In response to receiving a command to examine the debug symbol data from the incremental file, the preload symbol list is searched for the requested debug symbol data.

Abstract: The present disclosure provides a computer-implemented method for encoding video. The method includes: receiving a video frame for processing; generating one or more coding units of the video frame; and processing one or more coding units using one or more palette predictors having palette entries, wherein each palette entry of the one or more palette predictors has a corresponding reuse flag, and wherein a number of reuse flags for each palette predictor is set to a fixed number for a corresponding coding unit.

Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

Abstract: A controller for controlling an electric motor module equipped with incremental encoder and operation method thereof are provided. The controller includes a quadruple frequency circuit, a driver circuit, a non-volatile memory (NVM) and a multi-phase control circuit. The multi-phase control circuit can perform multi-phase control with aid of the NVM, for example: reading an offset counter value from the NVM; executing an initial angle estimation procedure, generating an initial counter value according to an estimated initial angle and the offset counter value, and starting utilizing the driver circuit to directly control the electric motor to start with the estimated initial angle and utilizing a counter to perform counting operations; calculating a counter value error and clear the current counter value to be zero; and performing compensation corresponding to a predetermined compensation times count according to the counter value error, respectively, to control the rotor to reach a target angle.

Abstract: A data query method based on Doris includes: acquiring history data in a bottom operator in a storage engine architecture of the Doris, and performing an aggregation calculation on the history data to obtain an aggregation result of the history data; caching, by a preset cache system, the aggregation result of the history data; performing an aggregation calculation on real-time data in a newly inserted bottom operator in the Doris, in response to a data query request, to obtain an aggregate result of the real-time data; acquiring the aggregation result of the history data from the preset cache system, and merging the aggregation result of the history data with the aggregation result of the real-time data to obtain merged data; and sending, by a data sending operator in the Doris, the merged data to an upper layer of an execution engine, to output a final data query result.

Abstract: The embodiments of the disclosure are applicable to the technical field of blockchain and provide a consensus trusted cluster changing method, a computer device and a computer-readable storage medium. The method is applicable to a blockchain and includes: determining a current epoch of a newly added validator node of the consensus trusted cluster in the blockchain and a target epoch of the consensus trusted cluster; requesting target status information and proof of target cluster change from a target validator node in the target epoch; verifying the target status information according to the proof of target cluster change; and updating, in case where the target status information has been verified, status information of the newly added validator node according to the target status information to complete change of the consensus trusted cluster. Through the above method, a trusted synchronization target status may be determined.

Abstract: The embodiments of the present disclosure provide a detection method, apparatus for automatic driving sensor, and electronic device. The method includes: pre-establishing a standard association relationship, the sensor to-be-detected is used for capturing in a fixed scene, and a corresponding capturing result is displayed.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A method for manufacturing a semiconductor structure is provided. A first layout is received, wherein the first layout comprises at least a pattern of an active region extending in a first direction. A second layout comprising a plurality of gate patterns extending in a second direction substantially perpendicular to the first direction is received, wherein distances between adjacent gate patterns are substantially consistent among the plurality of gate patterns. The first layout and the second layout are overlapped, thereby forming a plurality of transistor patterns. One of the plurality of gate patterns is shifted toward a source of one of the transistor patterns to form a third layout. A first photomask including the third layout is formed. The third layout of the photomask is transferred to form a plurality of gate structures over a substrate. A semiconductor structure thereof is also provided.

Abstract: An electrically controlled depolarizer based on a crossed-slit waveguide (3) includes a horizontal-slit waveguide (1), a 45-degree polarization rotation waveguide (2), a pair of modulation electrodes (4) and the crossed-slit waveguide (3).

Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.

Abstract: A method includes forming first semiconductor layers vertically stacked over a substrate; forming a gate structure over the first semiconductor layers; etching portions of the first semiconductor layers and the substrate uncovered by the substrate to form recesses; forming a spacer layer covering sidewalls of portions of the first semiconductor layers, while a bottommost one of the first semiconductor layers is uncovered by the spacer layer; etching the bottommost one of the first semiconductor layers to form a gap; forming a blocking dielectric in the gap; and forming source/drain epitaxy structures in the recesses and on opposite sides of the gate structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Abstract: A semiconductor device includes multiple transistors formed in a substrate, a frontside power rail disposed on a frontside of the substrate, and a backside power rail disposed on a backside of the substrate. The transistors form at least a first cell functioning under a first power supply voltage and a second cell functioning under a second power supply voltage that is different from the first power supply voltage. The frontside power rail provides the first power supply voltage to the first cell, and the backside power rail provides the second power supply voltage to the second cell.

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.

Abstract: A semiconductor device includes a channel region, first and second S/D contacts, first and second S/D epitaxial regions, a gate structure, and a gate contact. The channel region includes a first surface, a second surface opposite to the first surface, and a sidewall connected to the first surface and the second surface. The first S/D contact is disposed over the first surface of the channel region, the second S/D contact is disposed underneath the second surface of the channel region, the first S/D epitaxial region underlies the first S/D contact and overlies the first surface of the channel region, and the second S/D epitaxial region overlies the second S/D contact and underlies the second surface of the channel region. The gate structure surrounds the sidewall of the channel region, and the gate contact is disposed in proximity to the second S/D contact and lands on the gate structure.

Abstract: A method includes forming a first semiconductor layer over a substrate; forming a dummy material covering a first sidewall of the first semiconductor layer; forming source/drain epitaxy structures over the substrate and in contact with the first semiconductor layer; forming an interfacial layer on a top surface and a second sidewall of the first semiconductor layer that are uncovered by the dummy material; removing the dummy material to expose the first sidewall of the first semiconductor layer; forming a second semiconductor layer on the first sidewall of the first semiconductor layer after removing the dummy material, in which the second semiconductor layer and the source/drain epitaxy structures have different conductivity types; and forming a gate electrode over the interfacial layer.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.