Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure in a first p-type device region and a second fin structure in a second p-type device region. Each of the first fin structure and the second fin structure includes alternatingly stacking first semiconductor layers and second semiconductor layers. The method also includes etching the first fin structure and the second fin structure to form a first recess and a second recess, respectively, forming a first patterned mask layer to cover the second p-type device region, laterally recessing the second semiconductor layers of the first fin structure to form first notches, removing the first patterned mask layer, forming a first p-type source/drain feature in the first recess and the notches, and forming a second p-type source/drain feature in the second recess.

Abstract: A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; a first source/drain region over the first insulating layer, wherein the first source/drain region includes a first semiconductor layer extending continuously over the sidewalls of the first nanostructures, wherein the first semiconductor layer is a first semiconductor material and a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is a second semiconductor material different from the first semiconductor material.

Abstract: A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

Abstract: A chip package includes a semiconductor substrate, an isolation layer, a redistribution layer, a first protection layer, a second protection layer, and a land conductive structure. The semiconductor substrate has a sensing area, a conductive pad, and a through hole. The redistribution layer is located on the isolation layer, and includes a first section and a second section. The first protection layer is located on the first section, and is located on the isolation layer between the first and second sections. The second protection layer is disposed along the surface of the first protection layer. The transmittance of the first protection layer is less than that of the second protection layer. The land conductive structure is located on the second protection layer and in electrical contact with the redistribution layer.

Abstract: A controller for controlling an electric motor module equipped with incremental encoder and operation method thereof are provided. The controller includes a quadruple frequency circuit, a driver circuit, a non-volatile memory (NVM) and a multi-phase control circuit. The multi-phase control circuit can perform multi-phase control with aid of the NVM, for example: reading an offset counter value from the NVM; executing an initial angle estimation procedure, generating an initial counter value according to an estimated initial angle and the offset counter value, and starting utilizing the driver circuit to directly control the electric motor to start with the estimated initial angle and utilizing a counter to perform counting operations; calculating a counter value error and clear the current counter value to be zero; and performing compensation corresponding to a predetermined compensation times count according to the counter value error, respectively, to control the rotor to reach a target angle.

Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: An LED filament light bulb includes a bulb base, a driving circuit module mounted to the bulb base and including two electrical contacts, a bulb member, a light-emitting unit, and a first heat dissipation gel. The light-emitting unit includes at least two light-emitting strip modules, each including first and second conductive tabs. The first conductive tab of one light-emitting strip module is electrically connected to the second conductive tab of another light-emitting strip module. The second conductive tab of the one light-emitting strip module and the first conductive tab of the another light-emitting strip module are electrically and respectively connected to the electrical contacts. The first heat dissipation gel is disposed between the bulb member and the bulb base, and covers at least a portion of the driving circuit module.

Abstract: Systems, methods, devices, computer readable instruction media, and other embodiments are described for automated image processing and insight presentation. One embodiment involves receiving a plurality of ephemeral content messages from a plurality of client devices, and processing the messages to identify content associated with at least a first content type. A set of analysis data associated with the first content type is then generated from the messages, and portions of the messages associated with the first content type are processed to generate a first content collection. The first content collection and the set of analysis data are then communicated to a client device configured for a display interface comprising the first content collection and a representation of at least a portion of the set of analysis data.

Abstract: A wireless sensing method and systems based on compressed beamforming reports (CBR) are provided. The method includes performing channel sounding and transmit (TX) beamforming; performing sniffing or extracting information from Wi-Fi traffic; and performing multi-path estimation. The performing multi-path estimation includes performing multi-path modeling with CBR to analyze relationship between signal propagation characteristics and information in CBR by modeling a multi-path channel based on uplink and downlink steering matrices. The performing multi-path modeling with CBR includes performing multi-path modeling with CBR from physical paths to channel state information (CSI) and subsequently from CSI to CBR. The performing multi-path estimation further includes performing maximum likelihood multi-path estimation.

Abstract: A motor system includes a brushless direct current motor, voltage divider circuits, a switch and an analog-to-digital converter. The brushless direct current motor includes 3 sets of windings, one set of windings being floating during each commutation. There are 3 voltage divider circuits, and each voltage divider circuit includes a first resistor, a second resistor and a bypass diode. The first resistor includes a first terminal coupled to the set of floating windings. The second resistor includes a first terminal coupled to the first resistor, and a second terminal coupled to the switch to receive a control voltage at the second terminal of the second terminal or grounding the second terminal of the second terminal. The bypass diode is coupled in parallel to the first resistor. The analog-to-digital converter receives a divided back-electromotive force signal to determine back-electromotive force zero crossing, so as to perform the commutation.

Abstract: An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.

Abstract: The present disclosure provides a carrier for promoting Fenton reaction and the preparation process and uses thereof. The carrier for promoting Fenton reaction of the present disclosure achieves the effect of enhancing gene delivery efficiency and gene therapy for cancer through various efficacy experiments.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.