Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and semiconductor material layers stacked along a first direction over the substrate and spaced apart from each other. The semiconductor structure also includes inner spacers stacked along the first direction in spaces between the semiconductor material layers and a gate structure extending along a second direction and wrapping around the semiconductor material layers. In addition, the gate structure abuts a first side of the inner spacers. The semiconductor structure also includes a source/drain structure formed over the isolating feature and abutting the second side of the inner spacers.

Abstract: In various embodiments described herein, a visualization system receives message requests from client devices, wherein the message requests comprise at least location data that identifies a location of a client device, and media content, wherein the media content includes at least one of image data, audio data, and video data. In response to receiving the message requests that comprise the media content, the visualization system analyzes and parses the media content to detect one or more tags embedded within the media content. In response to detecting the tag, the visualization system identifies a campaign or account referenced by or associated with the tag. Based on the identification of the campaign based on the tag within the media content, the visualization system determines a distribution of the campaign based on the location data from the message request.

Abstract: Systems, methods, devices, computer readable instruction media, and other embodiments are described for automated image processing and insight presentation. One embodiment involves receiving a plurality of ephemeral content messages from a plurality of client devices, and processing the messages to identify content associated with at least a first content type. A set of analysis data associated with the first content type is then generated from the messages, and portions of the messages associated with the first content type are processed to generate a first content collection. The first content collection and the set of analysis data are then communicated to a client device configured for a display interface comprising the first content collection and a representation of at least a portion of the set of analysis data.

Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

Abstract: A method and an electronic device for detecting a vehicle queue length are disclosed. The method includes: when determining that a traffic light turns green, obtaining vehicle information of each vehicle on a lane section to be detected in a first preset time period before a time point when the traffic light turns green; determining at least one vehicle that has a static position and a static time point on the lane section to be detected; determining a first queuing vehicle and a last queuing vehicle on the lane section to be detected based on the at least one vehicle that has the static position and the static time point on the lane section to be detected; and determining a vehicle queue length on the lane section to be detected based on a position of the first queuing vehicle and a position of the last queuing vehicle.

Abstract: A mini LED chip and a manufacturing method thereof are provided. The mini LED chip includes a growth substrate and a light-emitting epitaxial layer including a first type semiconductor layer, a luminous layer, and a second type semiconductor layer. The second type semiconductor layer and the luminous layer include an electrode contact hollow part that exposes the first type semiconductor layer. Further, the mini LED chip includes a transparent conductive layer disposed on a side of the second type semiconductor layer facing away from the growth substrate, an extended electrode disposed on a side of the transparent conductive layer facing away from the growth substrate, an insulating and isolating reflection layer covering the electrode contact hollow part and an exposed surface of the transparent conductive layer and the extended electrode facing away from the growth substrate, and a first bonding electrode and a second bonding electrode.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a fin structure protruding from the substrate. The semiconductor structure also includes nanostructures formed over the fin structure and a gate structure surrounding the nanostructures. The semiconductor structure also includes a source/drain structure connected to the nanostructures and an isolating feature sandwiched between the fin structure and the source/drain structure.

Abstract: A method and apparatus for adjusting channelization of a traffic intersection are proposed. The specific implementation of the method is: obtaining a first traffic characteristic of vehicles at each of a plurality of target positions in a process of vehicles in a target traveling direction traveling through the traffic intersection from upstream to downstream in a preset first time period; generating first traffic change information of the traffic intersection based on the first traffic characteristic at each of the plurality of target positions; and in response to that the first traffic change information satisfies a preset first change distribution, generating channelization adjustment information for non-motorized vehicle lanes of the traffic intersection.

Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.

Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

Abstract: Systems, devices, media, and methods are presented for graphical icon identification within an image or video stream. The systems and methods receive an image including a graphical icon. The systems and methods identify a set of proposed regions of the image, at least one proposed region of the set of proposed regions containing the graphical icon and extract a set of semantic features for each proposed region of the set of proposed regions. Based on the set of semantic features of the set of proposed regions, the systems and methods identify a set of proposed icons corresponding to the graphical icon included in the image and determine a match between the graphical icon and at least one proposed icon of the set of proposed icons.