Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate doped with a first ion, a deep trench structure disposed in the substrate, a barrier doped region disposed on a top of the substrate and the deep trench structure, a first epitaxial layer disposed on the barrier doped region, a body region disposed in the first epitaxial layer, a source region disposed in the body region, a gate structure disposed in the first epitaxial layer, and a collector region disposed at a bottom of the substrate. By means of the semiconductor structure, performance of an insulated gate bipolar transistor can be improved.

Abstract: The present disclosure discloses a remote login processing method, apparatus, device and storage medium for an unmanned vehicle, and relates to the technical field of remote control. The implementation method of the specific method includes: sending a login request to an unmanned vehicle terminal through a first communication channel in response to a the login request received from an operator, and waiting to receive a reply instruction returned by the unmanned vehicle terminal; returning the reply instruction to the operator through the second communication channel in response to the reply instruction received from the unmanned vehicle terminal, so that the operator logs in the unmanned vehicle terminal according to the reply instruction, where there is a persistent connection state that unidirectionally authenticated between the second communication channel and the unmanned vehicle terminal.

Abstract: An IGBT device and a method for manufacturing it, the device includes a super junction structure that has several N-type pillars and P-type pillars arranged alternately; a cell unit that is located in an N-type epitaxial layer, and the N-type epitaxial layer is located above the N-type substrate; each cell unit includes a trench gate, a P-type body region, and a source region; an N-type carrier injection layer, the N-type carrier injection layer is located in the N-type epitaxial layer, and the N-type carrier injection layer is spaced apart from the N-type substrate by the N-type epitaxial layer; the bottom of the P-type body region is located in the N-type carrier injection layer; and a collector region that is located at the bottom of the N-type substrate.

Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.

Abstract: Systems, methods, devices, computer readable instruction media, and other embodiments are described for automated image processing and insight presentation. One embodiment involves receiving a plurality of ephemeral content messages from a plurality of client devices, and processing the messages to identify content associated with at least a first content type. A set of analysis data associated with the first content type is then generated from the messages, and portions of the messages associated with the first content type are processed to generate a first content collection. The first content collection and the set of analysis data are then communicated to a client device configured for a display interface comprising the first content collection and a representation of at least a portion of the set of analysis data.

Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.

Abstract: Embodiments of the present disclosure provide semiconductor devices having a front side to backside conductive path through a source/drain feature. In some embodiments, the front side to backside conductive path may be formed through a source/drain feature in a standard cell. The other embodiments, the front side to backside conductive path is formed through a source/drain feature in a filler cell. The front side to backside conductive path enables flexible routing for local connections, backside signal connections, and/or backside power rail connection.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

Abstract: In various embodiments described herein, a visualization system receives message requests from client devices, wherein the message requests comprise at least location data that identifies a location of a client device, and media content, wherein the media content includes at least one of image data, audio data, and video data. In response to receiving the message requests that comprise the media content, the visualization system analyzes and parses the media content to detect one or more tags embedded within the media content. In response to detecting the tag, the visualization system identifies a campaign or account referenced by or associated with the tag. Based on the identification of the campaign based on the tag within the media content, the visualization system determines a distribution of the campaign based on the location data from the message request.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.

Abstract: A time-segmented signal timing method is related to the field of intelligent transportation. The specific implementation is: obtaining traffic volume data of a target intersection in each period of time of N consecutive days, N being an integer greater than 1; performing curve fitting on the traffic volume data to determine a traffic volume curve corresponding to the target intersection of each day; determining calculating respective target points in the traffic volume curve with second derivatives satisfying a preset condition; and performing time-segmented signal timing on a traffic light at the target intersection based on time points corresponding to the respective target points.

Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate and directly contacting a bottom surface of the first source/drain feature.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.