Abstract: A system for measuring an overlay error of a sample is disclosed. The system may include a broadband illumination source configured to emit broadband illumination. The system may also include one or more optical elements configured to direct the broadband illumination to a target disposed on the sample, wherein the one or more optical elements are configured to collect illumination from the target and direct it to a spectrometer, wherein the spectrometer is configured to disperse multiple wavelengths of the illumination collected from the sample to multiple elements of a sensor to generate a plurality of signals. The system may also include a controller configured to calculate an overlay error between a first structure and a second structure of the target by comparing the plurality of signals with a plurality of calculated signals.

Abstract: A system may include illumination optics to direct an illumination beam to a sample at an off-axis angle, collection optics to collect scattered light from the sample, and a phase mask located at a first pupil plane to provide different phase shifts for light in two or more pupil regions of a collection area to reshape a point spread function of light scattered from one or more particles on a surface of the sample. The system may further include a polarization rotator located at a second pupil plane, where the polarization rotator provides a spatially-varying polarization rotation angle selected to rotate light scattered from the surface of the sample to a selected polarization angle, a polarizer to reject light polarized along the selected polarization angle, and a detector to generate a dark-field image of the sample based on light passed by the polarizer.

Abstract: Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

Abstract: A method for fabricating a semiconductor device includes forming a vertical field-effect transistor (FET) device including a plurality of first fin structures in a vertical FET device area of a substrate, and forming an input/output (IO) FET device including at least two second fin structures in an IO FET device area of the substrate. The at least two fin structures are connected by a channel having a length determined based on at least one voltage for implementing the IO FET device. Forming the vertical FET and IO FET devices includes selectively exposing a portion of the IO FET device area by selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.

Abstract: A dark-field inspection system may include an illumination source to generate an illumination beam, illumination optics configured to direct the illumination beam to a sample at an off-axis angle along an illumination direction, collection optics to collect scattered light from the sample in response to the illumination beam in a dark-field mode, a polarization rotator located at a pupil plane of the one or more collection optics, where the polarization rotator provides a spatially-varying polarization rotation angle selected to rotate light scattered from a surface of the sample to a selected polarization angle, a polarizer aligned to reject light polarized along the selected polarization angle to reject the light scattered from a surface of the sample, and a detector to generate a dark-field image of the sample based on scattered light from the sample passed by the polarizer.

Abstract: The present disclosure provides a thermoforming method and a thermoforming device for a glass product. The method comprises the following steps of: providing a thermoforming mold, wherein the thermoforming mold comprises a lower mold and an upper mold arranged above the lower mold and matched therewith, and providing a mold opening component; a pressurizing process, wherein a glass sheet placed in the thermoforming mold and at a softening point temperature and above is hot-pressed to form a glass product; a cooling process, wherein the glass product placed in the thermoforming mold is cooled, and when the temperature of the glass product drops to a glass point transformation temperature and below, the upper mold is opened by the mold opening component so that the upper mold is separated from the lower mold; and taking the glass product out when the temperature of the glass product in the thermoforming mold drops to a room temperature.

Abstract: The present disclosure relates to a thermoforming method, a thermoforming mold, and a thermoforming device.

Abstract: A method for detecting a lithium separation phenomenon of a battery of a terminal device is provided. The method includes detecting a working state of the battery, and collecting a first voltage of the battery when the working state of the battery is the resting state. The method further include collecting a second voltage of the battery when the battery is left to stand for a preset period of time, and determining whether the lithium separation phenomenon has occurred according to the first voltage and the second voltage. The implementation of the application can detect whether the lithium separation phenomenon has occurred in the battery and trigger a protection circuit of the battery in time when the lithium separation phenomenon has occurred in the battery.

Abstract: A semiconductor device includes a substrate having an input/output (IO) field-effect transistor (FET) device area, and an IO FET device formed in the IO FET device area. The IO FET device includes at least two fin structures separated by a distance associated with a length of a channel connecting the at least two fin structures. The length of the channel is determined based on at least one voltage for implementing the IO FET device.

Abstract: High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.

Abstract: The disclosure provides a method, an apparatus, and a device for calculating a short-circuit current of a battery. The method includes: obtaining an integral state of charge and a current state of charge of the battery; calculating a first difference based on the integral state of charge and the current state of charge; calculating the short-circuit current of the battery based on the first difference; obtaining a first real state of charge and a second real state of charge; updating the first real state of charge and the second real state of charge based on a temperature-impedance table and the short-circuit current of the battery; calculating a second difference based on the updated first real state of charge and the updated second real state of charge; and updating the short-circuit current of the battery based on the second difference.

Abstract: An electronic device includes a cell, a circuit board, and a cell protection unit. The circuit board is provided in the electronic device and configured to control the electronic device. The circuit board is electrically coupled to the cell, and the cell protection unit is provided on the circuit board. The cell protection unit is integrated with the circuit board, so as to facilitate heat dissipation of the cell, prolong the service life of the cell, speed up the production cycle of the cell, and reduce the production cost of the cell.

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

Abstract: A dark-field inspection system may include an illumination source to generate an illumination beam, illumination optics configured to direct the illumination beam to a sample at an off-axis angle along an illumination direction, collection optics to collect scattered light from the sample in response to the illumination beam in a dark-field mode, a polarization rotator located at a pupil plane of the one or more collection optics, where the polarization rotator provides a spatially-varying polarization rotation angle selected to rotate light scattered from a surface of the sample to a selected polarization angle, a polarizer aligned to reject light polarized along the selected polarization angle to reject the light scattered from a surface of the sample, and a detector to generate a dark-field image of the sample based on scattered light from the sample passed by the polarizer.

Abstract: A photocathode utilizes an field emitter array (FEA) integrally formed on a silicon substrate to enhance photoelectron emissions, and a thin boron layer disposed directly on the output surface of the FEA to prevent oxidation. The field emitters are formed by protrusions having various shapes (e.g., pyramids or rounded whiskers) disposed in a two-dimensional periodic pattern, and may be configured to operate in a reverse bias mode. An optional gate layer is provided to control emission currents. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the second boron layer. An optional external potential is generated between the opposing illuminated and output surfaces. An optional combination of n-type silicon field emitter and p-i-n photodiode film is formed by a special doping scheme and by applying an external potential. The photocathode forms part of sensor and inspection systems.

Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.

Abstract: A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.

Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.