Abstract: Optimization of optical parametric models for structural analysis using optical critical dimension metrology is described. A method includes determining a first optical model fit for a parameter of a structure. The first optical model fit is based on a domain of quantities for a first model of the structure. A first near optical field response is determined for a first quantity of the domain of quantities and a second near optical field response is determined for a second, different quantity of the domain of quantities. The first and second near optical field responses are compared to locate a common region of high optical field intensity for the parameter of the structure. The first model of the structure is modified to provide a second, different model of the structure. A second, different optical model fit is determined for the parameter of the structure based on the second model of the structure.

Abstract: A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.

Abstract: The present disclosure relates to a thermoforming method, a thermoforming mold, and a thermoforming device.

Abstract: The present disclosure provides a thermoforming method and a thermoforming device for a glass product. The method comprises the following steps of: providing a thermoforming mold, wherein the thermoforming mold comprises a lower mold and an upper mold arranged above the lower mold and matched therewith, and providing a mold opening component; a pressurizing process, wherein a glass sheet placed in the thermoforming mold and at a softening point temperature and above is hot-pressed to form a glass product; a cooling process, wherein the glass product placed in the thermoforming mold is cooled, and when the temperature of the glass product drops to a glass point transformation temperature and below, the upper mold is opened by the mold opening component so that the upper mold is separated from the lower mold; and taking the glass product out when the temperature of the glass product in the thermoforming mold drops to a room temperature.

Abstract: Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.

Abstract: Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.

Abstract: An electron source is formed on a silicon substrate having opposing first and second surfaces. At least one field emitter is prepared on the second surface of the silicon substrate to enhance the emission of electrons. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitter using a process that minimizes oxidation and defects. The field emitter can take various shapes such as pyramids and rounded whiskers. One or several optional gate layers may be placed at or slightly lower than the height of the field emitter tip in order to achieve fast and accurate control of the emission current and high emission currents. The field emitter can be p-type doped and configured to operate in a reverse bias mode or the field emitter can be n-type doped.

Abstract: A focusing EBCCD includes a control device positioned between a photocathode and a CCD. The control device has a plurality of holes therein, wherein the plurality of holes are formed perpendicular to a surface of the photocathode, and wherein a pattern of the plurality of holes is aligned with a pattern of pixels in the CCD. Each hole is surrounded by at least one first electrode, which is formed on a surface of the control device facing the photocathode. The control device may include a plurality of ridges between the holes. The control device may be separated from the photocathode by approximately half a shorter dimension of a CCD pixel or less. A plurality of first electrodes may be provided, wherein each first electrode surrounds a given hole and is separated from the given hole by a gap.

Abstract: An electron source is formed on a silicon substrate having opposing first and second surfaces. At least one field emitter is prepared on the second surface of the silicon substrate to enhance the emission of electrons. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitter using a process that minimizes oxidation and defects. The field emitter can take various shapes such as pyramids and rounded whiskers. One or several optional gate layers may be placed at or slightly lower than the height of the field emitter tip in order to achieve fast and accurate control of the emission current and high emission currents. The field emitter can be p-type doped and configured to operate in a reverse bias mode or the field emitter can be n-type doped.

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

Abstract: A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.

Abstract: A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Abstract: Methods and systems for performing broadband spectroscopic metrology with reduced sensitivity to focus errors are presented herein. Significant reductions in sensitivity to focus position error are achieved by imaging the measurement spot onto the detector such that the direction aligned with the plane of incidence on the wafer surface is oriented perpendicular to the direction of wavelength dispersion on the detector surface. This reduction in focus error sensitivity enables reduced focus accuracy and repeatability requirements, faster focus times, and reduced sensitivity to wavelength errors without compromising measurement accuracy. In a further aspect, the dimension of illumination field projected on the wafer plane in the direction perpendicular to the plane of incidence is adjusted to optimize the resulting measurement accuracy and speed based on the nature of target under measurement.

Abstract: A multi-column electron beam device includes an electron source comprising multiple field emitters fabricated on a surface of a silicon substrate. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitters. The field emitters can take various shapes including a pyramid, a cone, or a rounded whisker. Optional gate layers may be placed on the output surface near the field emitters. The field emitter may be p-type or n-type doped. Circuits may be incorporated into the wafer to control the emission current. A light source may be configured to illuminate the electron source and control the emission current. The multi-column electron beam device may be a multi-column electron beam lithography system configured to write a pattern on a sample.

Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.