Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Abstract: Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

Abstract: A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Abstract: A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.

Abstract: Methods and systems for performing broadband spectroscopic metrology with reduced sensitivity to focus errors are presented herein. Significant reductions in sensitivity to focus position error are achieved by imaging the measurement spot onto the detector such that the direction aligned with the plane of incidence on the wafer surface is oriented perpendicular to the direction of wavelength dispersion on the detector surface. This reduction in focus error sensitivity enables reduced focus accuracy and repeatability requirements, faster focus times, and reduced sensitivity to wavelength errors without compromising measurement accuracy. In a further aspect, the dimension of illumination field projected on the wafer plane in the direction perpendicular to the plane of incidence is adjusted to optimize the resulting measurement accuracy and speed based on the nature of target under measurement.

Abstract: A multi-column electron beam device includes an electron source comprising multiple field emitters fabricated on a surface of a silicon substrate. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitters. The field emitters can take various shapes including a pyramid, a cone, or a rounded whisker. Optional gate layers may be placed on the output surface near the field emitters. The field emitter may be p-type or n-type doped. Circuits may be incorporated into the wafer to control the emission current. A light source may be configured to illuminate the electron source and control the emission current. The multi-column electron beam device may be a multi-column electron beam lithography system configured to write a pattern on a sample.

Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

Abstract: A multi-column electron beam device includes an electron source comprising multiple field emitters fabricated on a surface of a silicon substrate. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitters. The field emitters can take various shapes including a pyramid, a cone, or a rounded whisker. Optional gate layers may be placed on the output surface near the field emitters. The field emitter may be p-type or n-type doped. Circuits may be incorporated into the wafer to control the emission current. A light source may be configured to illuminate the electron source and control the emission current. The multi-column electron beam device may be a multi-column electron beam lithography system configured to write a pattern on a sample.

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

Abstract: A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer.

Abstract: The present invention discloses an electronic product and LOGO display method and system thereof, wherein, the LOGO display system comprises an IR emitting and sensing module, a LOGO projection module and a processing module. It emits an IR and detects an IR intensity reflected by a human body through the IR emitting and sensing module; then compares the IR intensity detected by the IR emitting and sensing module with a threshold through the processing module, controls the LOGO projection module to project the LOGO, when the IR intensity is larger than the threshold; it has achieved a personalized display for the LOGO, and attracted an attention from the user to the LOGO, which is more energy-saving and environment-friendly than the prior art of displaying the LOGO continuously after turning on the machine.

Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

Abstract: An electron source is formed on a silicon substrate having opposing first and second surfaces. At least one field emitter is prepared on the second surface of the silicon substrate to enhance the emission of electrons. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitter using a process that minimizes oxidation and defects. The field emitter can take various shapes such as pyramids and rounded whiskers. One or several optional gate layers may be placed at or slightly lower than the height of the field emitter tip in order to achieve fast and accurate control of the emission current and high emission currents. The field emitter can be p-type doped and configured to operate in a reverse bias mode or the field emitter can be n-type doped.

Abstract: A photocathode utilizes an field emitter array (FEA) integrally formed on a silicon substrate to enhance photoelectron emissions, and a thin boron layer disposed directly on the output surface of the FEA to prevent oxidation. The field emitters are formed by protrusions having various shapes (e.g., pyramids or rounded whiskers) disposed in a two-dimensional periodic pattern, and may be configured to operate in a reverse bias mode. An optional gate layer is provided to control emission currents. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the second boron layer. An optional external potential is generated between the opposing illuminated and output surfaces. An optional combination of n-type silicon field emitter and p-i-n photodiode film is formed by a special doping scheme and by applying an external potential. The photocathode forms part of sensor and inspection systems.