Patents by Inventor Xuefeng Liu

Xuefeng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180108514
    Abstract: A multi-column electron beam device includes an electron source comprising multiple field emitters fabricated on a surface of a silicon substrate. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitters. The field emitters can take various shapes including a pyramid, a cone, or a rounded whisker. Optional gate layers may be placed on the output surface near the field emitters. The field emitter may be p-type or n-type doped. Circuits may be incorporated into the wafer to control the emission current. A light source may be configured to illuminate the electron source and control the emission current. The multi-column electron beam device may be a multi-column electron beam lithography system configured to write a pattern on a sample.
    Type: Application
    Filed: May 25, 2017
    Publication date: April 19, 2018
    Inventors: Yung-Ho Chuang, Yinying Xiao-Li, Xuefeng Liu, John Fielden
  • Publication number: 20180061754
    Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 1, 2018
    Inventors: Victor W.C. Chan, Xuefeng Liu, Yann A. M. Mignot, Yongan Xu
  • Publication number: 20170352621
    Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: Victor W. C. Chan, Xuefeng Liu, Yann A. M. Mignot, Yongan Xu
  • Patent number: 9837351
    Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Victor W. C. Chan, Xuefeng Liu, Yann A. M. Mignot, Yongan Xu
  • Patent number: 9786656
    Abstract: A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Xuefeng Liu, Junli Wang
  • Publication number: 20170206817
    Abstract: The present invention discloses an electronic product and LOGO display method and system thereof, wherein, the LOGO display system comprises an IR emitting and sensing module, a LOGO projection module and a processing module. It emits an IR and detects an IR intensity reflected by a human body through the IR emitting and sensing module; then compares the IR intensity detected by the IR emitting and sensing module with a threshold through the processing module, controls the LOGO projection module to project the LOGO, when the IR intensity is larger than the threshold; it has achieved a personalized display for the LOGO, and attracted an attention from the user to the LOGO, which is more energy-saving and environment-friendly than the prior art of displaying the LOGO continuously after turning on the machine.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 20, 2017
    Inventors: Kun XU, Zhenghua LU, Xuefeng LIU, Zhao LI
  • Patent number: 9657272
    Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 23, 2017
    Assignee: Georgetown University
    Inventors: Richard Schlegel, Xuefeng Liu
  • Publication number: 20170047207
    Abstract: An electron source is formed on a silicon substrate having opposing first and second surfaces. At least one field emitter is prepared on the second surface of the silicon substrate to enhance the emission of electrons. To prevent oxidation of the silicon, a thin, contiguous boron layer is disposed directly on the output surface of the field emitter using a process that minimizes oxidation and defects. The field emitter can take various shapes such as pyramids and rounded whiskers. One or several optional gate layers may be placed at or slightly lower than the height of the field emitter tip in order to achieve fast and accurate control of the emission current and high emission currents. The field emitter can be p-type doped and configured to operate in a reverse bias mode or the field emitter can be n-type doped.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 16, 2017
    Inventors: Yung-Ho Alex Chuang, Yinying Xiao-Li, Xuefeng Liu, John Fielden
  • Publication number: 20160343532
    Abstract: A photocathode utilizes an field emitter array (FEA) integrally formed on a silicon substrate to enhance photoelectron emissions, and a thin boron layer disposed directly on the output surface of the FEA to prevent oxidation. The field emitters are formed by protrusions having various shapes (e.g., pyramids or rounded whiskers) disposed in a two-dimensional periodic pattern, and may be configured to operate in a reverse bias mode. An optional gate layer is provided to control emission currents. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the second boron layer. An optional external potential is generated between the opposing illuminated and output surfaces. An optional combination of n-type silicon field emitter and p-i-n photodiode film is formed by a special doping scheme and by applying an external potential. The photocathode forms part of sensor and inspection systems.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 24, 2016
    Inventors: Yung-Ho Alex Chuang, John Fielden, Yinying Xiao-Li, Xuefeng Liu
  • Publication number: 20160289643
    Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.
    Type: Application
    Filed: February 10, 2016
    Publication date: October 6, 2016
    Inventors: Richard Schlegel, Xuefeng Liu
  • Publication number: 20160289644
    Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.
    Type: Application
    Filed: February 10, 2016
    Publication date: October 6, 2016
    Inventors: Richard Schlegel, Xuefeng Liu
  • Patent number: 9448162
    Abstract: A single-photon or ultra-weak light multi-D imaging spectral system and method. In order to realize rough time resolution, a time-resolved single-photon counting 2D imaging system for forming color or grey imaging is provided. Moreover, in order to realize high-precision time resolution, the system comprises a light source, an imaging spectral measurement unit, an electric detection unit, a system control unit and an algorithm unit. The light carrying information of an object is imaged on a spatial light modulator and randomly modulated according to compressed sensing theory, emergent light of a grating is collected using a point or array single-photon detector, the number of photons and photon arrival time are recorded, and reconstruction is carried out using the compressed sensing algorithm and related algorithm of the spectral imaging. The system provides single-photon detection sensitivity, high time resolution and wide spectral range, and can be applied in numerous new high-tech industries.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: September 20, 2016
    Assignee: Center for Space Science and Applied Research, Chinese Academy of Sciences
    Inventors: Guangjie Zhai, Wenkai Yu, Xuefeng Liu, Xuri Yao, Chao Wang, Zhibin Sun
  • Patent number: 9448184
    Abstract: Determination of one or more optical characteristics of a structure of a semiconductor wafer includes measuring one or more optical signals from one or more structures of a sample, determining a background optical field associated with a reference structure having a selected set of nominal characteristics based on the one or more structures, determining a correction optical field suitable for at least partially correcting the background field, wherein a difference between the measured one or more optical signals and a signal associated with a sum of the correction optical field and the background optical field is below a selected tolerance level, and extracting one or more characteristics associated with the one or more structures utilizing the correction optical field.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 20, 2016
    Assignee: KLA-Tencor Corporation
    Inventors: Xuefeng Liu, Yung-Ho Alex Chuang, John Fielden
  • Publication number: 20160245741
    Abstract: Methods and systems for performing broadband spectroscopic metrology with reduced sensitivity to focus errors are presented herein. Significant reductions in sensitivity to focus position error are achieved by imaging the measurement spot onto the detector such that the direction aligned with the plane of incidence on the wafer surface is oriented perpendicular to the direction of wavelength dispersion on the detector surface. This reduction in focus error sensitivity enables reduced focus accuracy and repeatability requirements, faster focus times, and reduced sensitivity to wavelength errors without compromising measurement accuracy. In a further aspect, the dimension of illumination field projected on the wafer plane in the direction perpendicular to the plane of incidence is adjusted to optimize the resulting measurement accuracy and speed based on the nature of target under measurement.
    Type: Application
    Filed: August 24, 2015
    Publication date: August 25, 2016
    Inventors: Shankar Krishnan, Guorong V. Zhuang, David Y. Wang, Xuefeng Liu
  • Patent number: 9404960
    Abstract: Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hanyi Ding, Xuefeng Liu, Alvin W. Strong, Randy L. Wolf
  • Patent number: 9310296
    Abstract: Optimization of optical parametric models for structural analysis using optical critical dimension metrology is described. A method includes determining a first optical model fit for a parameter of a structure. The first optical model fit is based on a domain of quantities for a first model of the structure. A first near optical field response is determined for a first quantity of the domain of quantities and a second near optical field response is determined for a second, different quantity of the domain of quantities. The first and second near optical field responses are compared to locate a common region of high optical field intensity for the parameter of the structure. The first model of the structure is modified to provide a second, different model of the structure. A second, different optical model fit is determined for the parameter of the structure based on the second model of the structure.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 12, 2016
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Thaddeus G. Dziura, Yung-Ho Chuang, Bin-ming Benjamin Tsai, Xuefeng Liu, John J. Hench
  • Patent number: 9304335
    Abstract: A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, William M. Green, Michael J. Hauser, Edward W. Kiewra, Xuefeng Liu, Steven M. Shank
  • Patent number: 9291554
    Abstract: Electromagnetic modeling of finite structures and finite illumination for metrology and inspection are described herein. In one embodiment, a method for evaluating a diffracting structure involves providing a model of the diffracting structure. The method involves computing background electric or magnetic fields of an environment of the diffracting structure. The method involves computing scattered electric or magnetic fields from the diffracting structure using a scattered field formulation based on the computed background fields. The method further involves computing spectral information for the model of the diffracting structure based on the computed scattered fields, and comparing the computed spectral information for the model with measured spectral information for the diffracting structure. In response to a good model fit, the method involves determining a physical characteristic of the diffracting structure based on the model of the diffracting structure.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 22, 2016
    Assignee: KLA-Tencor Corporation
    Inventors: Alexander Kuznetsov, Kevin Peterlinz, Andrei Shchegrov, Leonid Poslavsky, Xuefeng Liu
  • Patent number: 9279106
    Abstract: The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: March 8, 2016
    Assignee: Georgetown University
    Inventors: Richard Schlegel, Xuefeng Liu
  • Publication number: 20160018677
    Abstract: A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 21, 2016
    Inventors: John J. ELLIS-MONAGHAN, William M. GREEN, Michael J. HAUSER, Edward W. KIEWRA, Xuefeng LIU, Steven M. SHANK