Patents by Inventor Xueshi Yang

Xueshi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10353614
    Abstract: A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 16, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Xueshi Yang
  • Publication number: 20190179569
    Abstract: A data storage device includes a plurality of flash memories and at least one controller. Each of the flash memories includes a plurality of blocks. The controller operates the flash memories to access data in a plurality of working modes. The working mode of each flash memory is mutually independent. When the data storage device receives a control command from an application layer, the controller applies one of the working modes to one of the flash memories during operation, or switches the working mode of one of the flash memories during operation according to the control command.
    Type: Application
    Filed: August 2, 2018
    Publication date: June 13, 2019
    Inventor: Xueshi YANG
  • Patent number: 10191841
    Abstract: A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 29, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Xueshi Yang, Ningzhong Miao
  • Publication number: 20180364946
    Abstract: The invention relates to a data storage device and method, including at least one non-volatile storage and a controller with a two-layer structure. The two-layer structure includes a front end coupled to a host and a back end coupled to the non-volatile storage. The controller includes an instruction processor and at least one non-volatile storage controller. The instruction processor is arranged in the front end and communicates with the host and schedules operations of the data storage device in accordance with an external instruction. The non-volatile storage controller is arranged in the back end and controls the non-volatile storage in accordance with the schedule made by the instruction processor.
    Type: Application
    Filed: April 23, 2018
    Publication date: December 20, 2018
    Inventor: Xueshi YANG
  • Publication number: 20180336961
    Abstract: A data storage device with high security is disclosed. A nonvolatile memory provides a storage space divided into a plurality of first-level cells. The first-level cells are grouped into a plurality of second-level cells with each second-level cell containing several first-level cells. Each of the plurality of first-level cells is provided with checking and correcting code by a control unit. When reading a specified first-level cell, the control unit checks data in the specified first-level cell based on the checking and correcting code of the specified first-level cell and thereby performs a self-test on another space of a specified second-level cell. The specified first-level cell is provided in the specified second-level cell.
    Type: Application
    Filed: January 8, 2018
    Publication date: November 22, 2018
    Inventor: Xueshi YANG
  • Patent number: 10089196
    Abstract: A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 2, 2018
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Xueshi Yang
  • Publication number: 20180203813
    Abstract: A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.
    Type: Application
    Filed: September 29, 2015
    Publication date: July 19, 2018
    Inventor: Xueshi YANG
  • Patent number: 9997209
    Abstract: Provided are a power failure protection method and solid state drive (SSD). The SSD comprises: a power-failure detection device, for monitoring in real time whether the power supply is abnormal; a power-failure protection device performs a power-failure protection operation when the power supply is monitored to be abnormal: breaking a connection with a host system bus, an SSD internal clock breaking from a system bus clock and writing data in the SSD cache into a storage unit of the SSD by using the SSD internal clock. The technical solution ensures completion of the data protection operations by utilizing a remaining capacity, thus ensuring data integrity.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: June 12, 2018
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Xueshi Yang
  • Patent number: 9898413
    Abstract: An auto-adaptive system to implement partial write buffering for storage systems comprises: dynamically determining a wiring method for a data queue which needs to be written, and on the basis of a determination result, directly writing to a storage medium data suited to being written directly, and as for data suited for being written after being cached, caching the data by a caching device and then writing the data to the storage medium. A dynamic caching system uses the above method. The method and system significantly reduce the space requirements for caching, enable fault tolerance integration, and improve system performance.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 20, 2018
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Xueshi Yang
  • Publication number: 20170344474
    Abstract: A storage device metadata management method includes: a superblock is formed of at least one erase block; the superblock reserves a space for storing metadata related to the superblock; the metadata includes a serial number distributed to the superblock and address mapping information in the superblock; the address mapping information stores a mapping relationship of a physical block address to a logic block address; when data is written into the superblock, the address mapping information corresponding to the data is also written into the superblock; when a system is recovered, a page table of the storage system is recovered according to the address mapping information of the superblock; the page table marks a mapping relationship of a logic block address to a physical block address. The method can ensure a complete recovery of the page table during startup and a normal operation of the storage device when started.
    Type: Application
    Filed: December 4, 2015
    Publication date: November 30, 2017
    Inventors: Zhen ZHOU, Xueshi YANG
  • Publication number: 20170330603
    Abstract: Provided are a power failure protection method and solid state drive (SSD) The SSD comprises: a power-failure detection device, for monitoring in real time whether the power supply is abnormal; a power-failure protection device performs a power-failure protection operation when the power supply is monitored to be abnormal: breaking a connection with a host system bus, an SSD internal clock breaking from a system bus clock and writing data in the SSD cache into a storage unit of the SSD by using the SSD internal clock. The technical solution ensures completion of the data protection operations by utilizing a remaining capacity, thus ensuring data integrity.
    Type: Application
    Filed: January 8, 2015
    Publication date: November 16, 2017
    Applicant: Shannon Systems Ltd.
    Inventors: Zhen ZHOU, Xueshi YANG
  • Publication number: 20170329522
    Abstract: “A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.
    Type: Application
    Filed: December 31, 2014
    Publication date: November 16, 2017
    Applicant: Shannon Systems Ltd.
    Inventor: Xueshi YANG
  • Patent number: 9720770
    Abstract: A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 1, 2017
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Xueshi Yang
  • Patent number: 9594630
    Abstract: A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 14, 2017
    Assignee: Marvell World Trade LTD.
    Inventors: Xueshi Yang, Zining Wu, Pantas Sutardja
  • Publication number: 20170017556
    Abstract: A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.
    Type: Application
    Filed: July 13, 2016
    Publication date: January 19, 2017
    Inventors: Zhen ZHOU, Xueshi YANG
  • Patent number: 9547444
    Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: January 17, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xueshi Yang, Chi Kong Lee
  • Publication number: 20170010962
    Abstract: A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 12, 2017
    Inventors: Xueshi YANG, Ningzhong MIAO
  • Patent number: 9542312
    Abstract: Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: January 10, 2017
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Xueshi Yang, Tony Yoon
  • Publication number: 20160283387
    Abstract: An auto-adaptive system to implement partial write buffering for storage systems comprises: dynamically determining a wiring method for a data queue which needs to be written, and on the basis of a determination result, directly writing to a storage medium data suited to being written directly, and as for data suited for being written after being cached, caching the data by a caching device and then writing the data to the storage medium. A dynamic caching system uses the above method. The method and system significantly reduce the space requirements for caching, enable fault tolerance integration, and improve system performance.
    Type: Application
    Filed: October 29, 2013
    Publication date: September 29, 2016
    Inventors: Zhen ZHOU, Xueshi YANG
  • Publication number: 20160224420
    Abstract: A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.
    Type: Application
    Filed: September 16, 2013
    Publication date: August 4, 2016
    Inventors: Zhen ZHOU, Xueshi YANG