Abstract: A system includes a detection module, an adjustment module, a phase shifter module, and a write module. The detection module: samples a sensor signal to generate a digital signal; based on the digital signal, detects a pattern of first bit islands on media; and based on the pattern, determines a phase error of the digital signal. The adjustment module generates a second clock signal based on the phase error and a first clock signal. The second clock signal is synchronized with start or end times of the first bit islands. The phase shifter module, based on a predetermined value, adjusts a phase of the second clock signal. The detection module samples the sensor signal based on the second clock signal with the adjusted phase. The write module, based on the second clock signal prior to being phase adjusted, writes data to the first bit islands or second bit islands.

Abstract: Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data.

Abstract: A system comprising a memory, and a control module external to the memory. The memory includes a plurality of cells. The control module is configured to receive user data to be stored in the plurality of cells, select one of a plurality of sequences of pilot data, based on the selected one of the plurality of sequences of pilot data, generate pilot data having a known predetermined sequence, combine the pilot data with the user data, and output the combined pilot data and user data. A write module is configured to write the combined pilot data and user data to the plurality of cells of the memory.

Abstract: Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method.

Abstract: Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of reference voltages that are near an integral reference voltage to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.

Abstract: A memory control module includes a read module configured to receive a first signal read from a first storage region of a memory cell, and receive a second signal read from a second storage region of the memory cell. A data detection module is configured to, based on a noiseless signal, detect respective data in each of the first storage region and the second storage region. The noiseless signal includes an ideal signal and an interference signal associated with at least one of the first signal and the second signal.

Abstract: Methods, systems and computer program products for performing hybrid defect detection are disclosed. In some implementations, an apparatus includes a signal module to process data signals corresponding to data on a storage medium to generate signal samples. The apparatus includes a first defect detector to identify a first portion of the signal samples, determine a number of the signal samples in the first portion that are associated with abnormal signal characteristics, and generate a first output based on the number of the signal samples in the first portion that are associated with abnormal signal characteristics. The apparatus includes a second defect detector to identify a second portion of the signal samples different from the first portion, and generate a second output based on a correlation between data bits and signal samples in the second portion.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.

Abstract: Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells are described. In some implementations, the memory cells can be programmed in a predetermined sequence that allows pages with the most-significant bit (MSB) and central significant bit (CSB) to be programmed first prior to programming pages with the least-significant bit (LSB). This sequence allows neighboring cells (e.g., cells neighboring a target cell) to be programmed first so as to reduce the floating gate coupling interference and threshold voltage drift on the target cell that is to be programmed in the subsequent stage. To accommodate the programming sequence (e.g., at the device level), additional buffer memories can be added.

Abstract: Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Abstract: Systems and methods are provided that use LDPC codes to determine the locations of insertions or deletions within bit-strings of information transmitted through communication channels and which notify a LDPC decoder of the locations of the insertions or deletions prior to the start of the decoding process. The use of such systems and methods, according to this disclosure, may improve LDPC decoder performance by reducing errors cause by insertions and/or deletions. The use of such systems and methods, according to this disclosure, may also provide improved application performance and larger data transmission rates.

Abstract: Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.

Abstract: A system including a read module and a detector module. The read module is configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line. The detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes one of a first signal and a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal accounts for interference from the second memory cell.

Abstract: A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory.

Abstract: An apparatus including: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block configured to compute at least optimal or near optimal detection threshold values of level distributions of the multi-level memory cells based, at least in part, on (i) the estimated mean values and (ii) the estimated standard deviation values, wherein the optimal or near optimal detection threshold values are to be used in order to facilitate reading of the data stored in the multi-level memory cells.

Abstract: Systems and techniques relating to control of magnetic devices are disclosed. A described technique includes receiving a waveform via a head about a recording medium which includes data tracks and servo regions, detecting a servo region based on the waveform becoming an alternating signal, which is indicative of the head's path over discrete radially arranged magnetic strips in the servo region; performing a frequency synchronization of a read clock based on the detection to establish a frequency lock; performing a phase synchronization of the read clock to align a phase of the read clock with respect to acquired samples of the alternating signal; performing a synchronization of a write clock based on a write of a test sequence to the medium, the write clock being responsive to the frequency lock and the read clock; and writing, using the synchronized write clock, data to the medium for servo control.

Abstract: A system including a reference voltage module configured to generate one or more reference voltages for determining states of a plurality of memory cells of a nonvolatile memory, where the plurality of memory cells have a threshold voltage distribution. A divider module divides, in response to a change in the threshold voltage distribution, a voltage range into a plurality of regions. An update module updates, to compensate for the change in the threshold voltage distribution, one of the reference voltages to a voltage value associated with one of the plurality of regions.

Abstract: The present disclosure includes systems and techniques relating to data type based alignment of data written to non-volatile memory. In some implementations, an apparatus includes an input, an output, and control logic coupled with the input and the output, where the control logic is configured to modify placement of data written to a non-volatile memory based on a first data type of the data. The first data type is distinct from a second data type also written to the non-volatile memory, and the placement of the data of the first data type is modified in relation to placement of data of the second data type in the non-volatile memory.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure containing a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a charge level, the two or more bits corresponding to two or more bit positions. The described system includes circuitry configured to monitor read-back data from the non-volatile memory structure, determine estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data, and adjust one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

Abstract: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector.