Abstract: A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.

Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.

Abstract: A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.

Abstract: Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.

Abstract: An auto-adaptive system to implement partial write buffering for storage systems comprises: dynamically determining a wiring method for a data queue which needs to be written, and on the basis of a determination result, directly writing to a storage medium data suited to being written directly, and as for data suited for being written after being cached, caching the data by a caching device and then writing the data to the storage medium. A dynamic caching system uses the above method. The method and system significantly reduce the space requirements for caching, enable fault tolerance integration, and improve system performance.

Abstract: A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.

Abstract: A system including a read module, a delay buffer, and a least mean square module. The read module is configured to read charge levels of memory cells of a nonvolatile memory and to generate read signals based on the charge levels of the memory cells of the nonvolatile memory. The delay buffer is configured to delay the read signals and to generate delayed read signals. The least mean square module is configured to generate mean values of the charge levels used to program the memory cells based on (i) differences between the read signals and the delayed read signals and (ii) a scaling factor. The scaling factor is based on variations in the charge levels due to cycling of the memory cells of the nonvolatile memory.

Abstract: A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values. The one or more of the interference values are selected based on (i) the state to which the memory cell is to be programmed, and (ii) the states of the one or more memory cells.

Abstract: A system including a read module and a detector module. The read module is configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line. The detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes one of a first signal and a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal accounts for interference from the second memory cell.

Abstract: A control module for a memory system including a plurality of multi-bit memory cells. The control module includes a read module configured to receive, from a first storage region of a first memory cell of the plurality of multi-bit memory cells, a first signal, and generate a second signal based on the first signal. A signal detection module is configured to determine distances between the second signal and respective estimates of a plurality of noiseless signals associated with the first memory cell. The noiseless signals correspond to a combination of an ideal signal and an interference signal. The signal detection module is further configured to determine, from the estimates of the plurality of noiseless signals, a noiseless signal that matches most closely to the second signal. A data conversion module is configured to detect data stored in the first storage region based on the noiseless signal that matches most closely to the second signal.

Abstract: Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.

Abstract: An apparatus including a memory array and control circuitry. The control circuitry is configured to, based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges. The control circuitry is further configured to, based at least on the number of memory cells that have threshold voltages in each of the plurality of voltage ranges, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage. The control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on the estimated offset amount.

Abstract: An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector.

Abstract: Adaptive memory read and write systems and methods are provided that may compute estimated means and variances of multi-level memory cells to facilitate writing and reading of data to and from the multi-level memory cells are described herein. The systems may include an apparatus comprising multi-level memory cells, and an estimation block configured to compute estimated means and variances of level distributions of the multi-level memory cells by processing signal samples provided by at least a subset of the multi-level memory cells, the estimated means and variances to be used to facilitate writing and/or reading of data to and/or from at least selected ones of the multi-level memory cells, the multi-level memory cells having M-levels where M is an integer greater than 1, and each of the level distributions is associated with a corresponding level of the M-levels.

Abstract: In one embodiment, a method comprises determining an adaptation for a reference voltage used in a flash memory device as a function of a first count of items read from the flash memory device and a second count of items read from the flash memory device; and shifting the reference voltage at least in part by the adaptation.

Abstract: Embodiments provide methods, apparatuses, and articles of manufacture that encode and decode data based on various error correction codes. In one embodiment, a method may include receiving input data, encoding the input data with an error correction code that is selected from a plurality of error correction codes based on the size of the input data, and writing the encoded input data to a memory device. The encoded data can be subsequently, retrieved and decoded when needed.

Abstract: This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for reducing the amount of hardware and processing resources of a flash controller to read an amount of data. These techniques effectively increase the speed at which flash memory can be read by the flash controller without modifying conventional flash memories.

Abstract: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector.

Abstract: Flash memory stored data modification is described. In embodiments, a flash memory system includes flash memory and a memory controller that manages data write and erase operations to the flash memory. The flash memory includes a first flash memory region of single-write flash memory cells that are each configured for a data write operation and a corresponding erase operation before a subsequent data write operation. The flash memory also includes a second flash memory region of multiple-write flash memory cells that are each configured for multiple data write operations before an erase operation.

Abstract: This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.