Patents by Inventor Xueshi Yang

Xueshi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patterned magnetic media synchronization systems
    Patent number: 8331050
    Abstract: A write clock synchronization system includes a channel module that reads a servo section of a bit-patterned magnetic medium to determine a preamble signal based on the servo section. An initial phase estimating system estimates an initial phase of the preamble signal based on servo clock samples of the preamble signal and estimates an initial phase of the preamble signal based on write clock samples of the preamble signal. A phase determination module estimates a phase of the write clock signal based on the initial phase of the preamble signal estimated using the servo clock samples and the initial phase of the preamble signal estimated using the write clock samples. A phase error module estimates a phase error based on the phase of the write clock signal. The channel module writes data to discontinuous bit islands of the bit-patterned magnetic medium based on the phase error.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: December 11, 2012
    Assignee: Marvell International Ltd.
    Inventors: Qiyue Zou, Xueshi Yang, Gregory Burd
  • BM/LLR computations for multi-dimensional TCM/BCM codes
    Patent number: 8327244
    Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: December 4, 2012
    Assignee: Marvell International Ltd.
    Inventors: Gregory Burd, Xueshi Yang
  • SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH
    Publication number: 20120300545
    Abstract: Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Zhengang Chen, Gregory Burd, Shashi Kiran Chilappagari, Xueshi Yang
  • Integrated 2-level low density parity check (LDPC) codes
    Patent number: 8321752
    Abstract: An encoding system includes a first low density parity check (LDPC) module and a second LDPC module. The first LDPC module is configured to generate a first encoded codeword by encoding a first codeword using a first LDPC code. The second LDPC module is configured to generate a second encoded codeword by encoding a second codeword using a second LDPC code. Signals based on the first encoded codeword and signals based on the second encoded codeword are transmitted over a communications channel. The first LDPC code is defined by a first parity check matrix and the second LDPC code is defined by a second parity check matrix. The second parity check matrix includes the first parity check matrix, a zero matrix, and a supplementary matrix.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: November 27, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Nedeljko Varnica
  • Defect detection design
    Patent number: 8315132
    Abstract: A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: November 20, 2012
    Assignee: Marvell International Ltd.
    Inventors: Shaohua Yang, Hongwei Song, Zining Wu, Xueshi Yang, Hongxin Song
  • Pilot placement for non-volatile memory
    Patent number: 8316206
    Abstract: A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: November 20, 2012
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu, Pantas Sutardja
  • Bit patterned magnetic media data format
    Patent number: 8315003
    Abstract: In an implementation, a media drive comprises bit patterned magnetic media and one or more modules. The one or more modules are to cause data to be written on the bit patterned magnetic media in a data sector that includes a synchronization mark disposed between data blocks of the data sector.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 20, 2012
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Data Compression and Compacting for Memory Devices
    Publication number: 20120290798
    Abstract: Embodiments of the present disclosure provide apparatuses and methods for determining a compacting arrangement to store logical addressable units, which include compressed data sectors, into hardware addressable units of a storage device. The compacting arrangement is based on compression information associated with the logical addressable units. A write module is used to write the compressed data sectors to the storage device according to the compacting arrangement.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 15, 2012
    Inventors: ChengKuo Huang, Siu-Hung Fred Au, Sean Lee, Fei Sun, Grace Pao Yi Chen, Man Cheung, Xueshi Yang
  • ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS
    Publication number: 20120278682
    Abstract: Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.
    Type: Application
    Filed: April 27, 2012
    Publication date: November 1, 2012
    Inventors: Xueshi Yang, Zining Wu
  • Data synchronization for bit insertion or deletion
    Patent number: 8300344
    Abstract: In an implementation, a media drive includes bit patterned magnetic media and a module. The module is to cause data encoded by one or more error correction codes to be written on the bit patterned magnetic media with a constraint that is configured to be used to synchronize the data if a bit insertion or deletion occurs.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 30, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Reference Voltage Optimization for Flash Memory
    Publication number: 20120236655
    Abstract: A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.
    Type: Application
    Filed: April 16, 2012
    Publication date: September 20, 2012
    Inventor: Xueshi Yang
  • Reprogramming non-volatile memory devices for read disturbance mitigation
    Patent number: 8264880
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described device includes a non-volatile memory structure including a first data area, and a second data area that stores information. The information can include a first value corresponding to the first data area, the first value being set responsive to a last programming cycle on the first data area, and a second value indicating a total number of programming or erasing operations on the first data area.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 11, 2012
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Systems and methods for performing concatenated error correction
    Patent number: 8266495
    Abstract: A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: September 11, 2012
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu, Seo-How Low
  • Error correction system using an iterative product code
    Patent number: 8255763
    Abstract: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. On the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. A portion of the first set of codewords is divided into a plurality of symbols which are encoded based on the embedded parity code. On the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information is used with other soft information by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: August 28, 2012
    Assignee: Marvell International Ltd.
    Inventors: Shaohua Yang, Zining Wu, Gregory Burd, Xueshi Yang, Hongwei Song, Nedeljko Varnica
  • RELIABILITY METRICS MANAGEMENT FOR SOFT DECODING
    Publication number: 20120213001
    Abstract: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 23, 2012
    Inventor: Xueshi Yang
  • Methods and apparatus for providing multilevel coset coding and probabilistic error correction
    Patent number: 8239731
    Abstract: Systems and methods are provided for performing multilevel coset coding and probabilistic error correction. Multiple bit data is encoded in a memory by combining one of the bit positions of multiple data values and encoding the combination to form a codeword. A data point containing a bit error is determined by decoding a codeword associated with one of the bit positions. A first coset corresponding to a data point with the error is determined where the coset includes labels representing non-adjacent analog signal levels. Labels in a second coset that includes mutually exclusive labels from the first coset are analyzed to select a label representing a signal level that is closest in proximity to the signal level represented by the data point containing the bit error than the other labels in the second coset. The data point error is corrected by replacing the data point with the selected label.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: August 7, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Mapping Data to Non-Volatile Memory
    Publication number: 20120198135
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 2, 2012
    Inventors: Shashi Kiran Chilappagari, Xueshi Yang, Gregory Burd
  • METHODS AND SYSTEMS FOR EFFICIENT DECODING OF CONCATENATED ERROR CORRECTION CODES
    Publication number: 20120198308
    Abstract: Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 2, 2012
    Inventors: Nedeljko Varnica, Xueshi Yang, Sashi Kiran Chilappagari
  • SOFT DECODING SYSTEMS AND METHODS FOR FLASH BASED MEMORY SYSTEMS
    Publication number: 20120198314
    Abstract: Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 2, 2012
    Inventors: Xueshi Yang, Gregory Burd
  • Programming method for multi-level cell flash for minimizing inter-cell interference
    Patent number: 8228728
    Abstract: Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells are described. In some implementations, the memory cells can be programmed in a predetermined sequence that allows pages with the most-significant bit (MSB) and central significant bit (CSB) to be programmed first prior to programming pages with the least-significant bit (LSB). This sequence allows neighboring cells (e.g., cells neighboring a target cell) to be programmed first so as to reduce the floating gate coupling interference and threshold voltage drift on the target cell that is to be programmed in the subsequent stage. To accommodate the programming sequence (e.g., at the device level), additional buffer memories can be added.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Zining Wu