Abstract: In a method for providing an estimate of a head position for a disk drive, a readback signal is filtered. The readback signal includes a first position signal component corresponding to a first position pattern on a disk, and includes a second position signal component corresponding to a second position pattern on the disk. Filtering the readback signal includes using a filter determined based on statistical information regarding a noise component of the readback signal. An estimate of an amplitude of the first position signal component is generated based on the filtered readback signal, and an estimate of an amplitude of the second position signal component is generated based on the filtered readback signal. An estimate of a head position with respect to a track on the disk is generated based on the estimate of the amplitude of the first position signal component and the estimate of the amplitude of the second position signal component.

Abstract: In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read or write speed requirements. A data block to be written may be considered an object, and is examined, and from its attributes one or more memory device operating modes may be determined, such as different numbers of bits per cell, different numbers of error-correction code (ECC) parities per user data block, and encryption vs. lack of encryption. The storage controller then performs the writing process according to the mode(s) of operation determined by the attributes. Respective designated portions of the storage device may be selectively operated in respective ones of a plurality of operating modes to process each of the plurality of data objects based on a corresponding one or more of the attributes.

Abstract: A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM.

Abstract: Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

Abstract: A parallel channel timing recovery circuit. The parallel timing recovery circuit comprises multiple prefilters receiving parallel channel outputs and providing prefilter outputs. Multiple sampling filters receive the prefilter outputs and provide multiple discrete time signal samples. A self-timing circuit has multiple inputs receiving the multiple discrete time signal samples. The self-timing circuit provides a sampling control output to the sampling filters. The sampling control output is based on a composite of the multiple discrete time signal samples. Each of the sampling filters generates a discrete time signal sample based on the sampling control output and the prefilter outputs.

Abstract: A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.

Abstract: Iterative decoding channel architectures employing coded modulation are provided. The coded modulation is realized via set partitioning for Partial Response (PR) channels along with multi-level coding. Associated error correction encoding and decoding methods, with additional compatibility considerations for channel constrained coding, are also provided.

Abstract: A memory system includes a first parameter estimation module that receives pilot signals that are generated based on pilot data stored in a memory. The first parameter estimate module generates a first estimate of a signal quality value associated with a block of the memory based on reference pilot information. A second parameter estimation module generates a second estimate of the signal quality value based on the first estimate and user data signals that are generated based on user data stored in the memory. A processing module generates recovered user data based on the second estimate.

Abstract: The present disclosure includes apparatus, systems and techniques relating to lossless data compression. In some implementations, an apparatus includes a memory module to store data. The memory module includes a first buffer portion to store encoded symbols of the data, and a second buffer portion to store symbols of the data to be encoded. The apparatus includes an encoder to compare the symbols stored in the second buffer portion with the encoded symbols stored in the first buffer portion and to compress the data. The encoder can operate in a first encoding mode to encode the symbols in the second buffer portion with corresponding codewords until detecting a repeated pattern of symbols in the second buffer portion that matches the encoded symbols in the first buffer portion. The encoder can operate in a second encoding mode responsive to detecting the repeated pattern.

Abstract: A storage device has a storage medium, a plurality of read-write mechanisms, a quality monitoring and book-keeping unit and a scheduling unit. The plurality of read-write mechanisms is coupled to the storage medium. The quality monitoring and book-keeping unit is coupled to the plurality of read-write mechanisms and is adapted to monitor at least one performance parameter associated with each read-write mechanism during operation. The scheduling unit is coupled to the quality monitoring and book-keeping unit. The scheduling unit is adapted to rank each of the plurality of read-write mechanisms according to the at least one performance parameter and to responsively schedule use of a read-write mechanism according to its rank.

Abstract: Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

Abstract: The present disclosure includes systems and techniques relating to a non-volatile memory that includes an internal data source. In some implementations, a device includes a buffer, a memory cell array, and processing circuitry coupled with the buffer and the memory cell array, and configured to selectively fill the buffer with auxiliary data from the internal data source specified by the controller and user data received from an external source, in response to instructions from the controller.

Abstract: A decoder that decodes Bose, Ray-Chaudhuri, Hocquenghem (BCH) codewords includes an inner decoding module that decodes inner codes of two dimensional BCH product codewords and that includes an error decoding module that computes error values, an outer decoding module that decodes outer codes of the two dimensional BCH product codewords, and an error correction module that employs the error decoding module to iteratively correct errors in the two-dimensional BCH product codewords.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. Systems and techniques can include obtaining information to store in a non-volatile memory, the information including a data segment, compressing data within the data segment, including pad data in one or more portions of the data segment based on a compression result attained by the compression, and writing data of the data segment.

Abstract: A method of reading a data block from a sector of a recording media is described. The data block from the sector of the recording channel is decoded with an ECC decoder (first trial). The data block is re-decoded (second trial) using an adjusted timing recovery block that is adjusted based on the decoded data block, if the number of errors exceeded an error correction capability of the ECC decoder on the first trial. In one embodiment, the data block is reread from the same sector of the recording channel using the adjusted timing recovery block that is adjusted based on the re-decoded data block. The data block is subsequently jointly decoded with the waveforms obtained from the second trial by a possibly modified sequence detector, if the number of errors exceeded the error correction capability of the ECC decoder during the second trial.

Abstract: Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.

Abstract: Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages.

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.

Abstract: Methods, apparatuses, systems, and architectures for providing fast, independent, and reliable retrieval of system data (e.g., metadata) from a storage system, which enables minimal degradation in the reliability of user data. Methods generally include encoding the system data at least twice, at least once independently and at least once jointly along with user data. Methods can also include decoding the system data first, and upon a decoding failure, jointly decoding the system data and the user data.