Abstract: Embodiments of the present disclosure provide methods and apparatus for providing a NAND flash memory arrangement that comprises a source select line (SSL), a drain select line (DSL) and a plurality of NAND memory cells arranged to provide a plurality of data pages. The method further includes defining a first set of data pages in close proximity to the SSL, defining a second set of data pages in close proximity to the DSL, and differentiating the first set of data pages and the second set of data pages from at least the remaining data pages.

Abstract: This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for determining whether or not a flash-memory cell has a high probability of an error by determining whether a voltage threshold is in close proximity to a reference voltage.

Abstract: This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.

Abstract: Systems and methods for jointly optimizing various parameters of an error-correction code (e.g., a product code or other multi-dimensional code) are provided. In certain embodiments, joint optimization of coverage assignments, configuration assignments, rate assignments, and/or user data length assignments of an error-correction code is performed so as to achieve desired error-protection performance at minimized implementation complexity. In certain embodiments, coverage assignments of an error-correction code are optimized to achieve a desired performance level with minimized implementation complexity.

Abstract: A memory system includes an array of X memory cells that each includes Y storage regions. The system also includes a read module that receives a first read signal that includes a first read signal data component and a first read signal interference component from a first one of the Y storage regions. The read module also receives a second read signal from a second one of the Y storage regions. The first interference component includes interference from the second one of the Y storage regions. The system also includes a data detection module that recovers the first read signal data component from the first read signal based on the second read signal and one or more of M noiseless signal estimates. M and X are integers greater than or equal to one, and Y is an integer greater than or equal to two.

Abstract: A memory system includes a selector module that selects and switches between one of N sequences of signal levels for pilot data. The N sequences are different, and N is an integer greater than 1. A multiplexer module selectively combines data and the pilot data and outputs a combined signal. A write module writes to memory based on the combined signal.

Abstract: Systems and methods for decoding data using a hybrid decoder are provided. A data signal that includes a codeword is received. A signal quality indicator for the data signal is computed. One of a plurality of decoders is selected based on the computed signal quality indicator. Each of the plurality of decoders is configured to decode information based on a different decoding technique. The codeword included in the data signal is decoded using the selected one of the plurality of decoders.

Abstract: A memory system includes a state set module that provides a first state set having a plurality of states, each being assigned to represent a particular data sequence, and a second state set having a same number of states as the first state set, wherein an assignment of one or more particular data sequences among the states of the second state set is different relative to that set forth in the first state set. The memory system further includes a write module that writes first data to a first multi-level memory cell of the memory system based on the first state set, the first multi-level cell being located on a wordline of the memory system, and that writes second data to a second multi-level memory cell of the memory system based on the second state set, the second multi-level cell being located on the wordline of the memory system.

Abstract: Systems and methods are provided that use LDPC codes to determine the locations of insertions or deletions within bit-strings of information transmitted through communication channels and which notify a LDPC decoder of the locations of the insertions or deletions prior to the start of the decoding process. The use of such systems and methods, according to this disclosure, may improve LDPC decoder performance by reducing errors cause by insertions and/or deletions. The use of such systems and methods, according to this disclosure, may also provide improved application performance and larger data transmission rates.

Abstract: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

Abstract: Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data.

Abstract: Adaptive systems and methods that may help assure the reliability of data retrieved from memory cells are described herein. The systems may include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block may be configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block may be configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.

Abstract: A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.

Abstract: Embodiments provide a method comprising receiving input data comprising a plurality of data sectors; compressing the plurality of data sectors to generate a corresponding plurality of compressed data sectors; splitting a compressed data sector of the plurality of compressed data sectors to generate a plurality of split compressed data sectors; and storing the plurality of compressed data sectors, including the plurality of split compressed data sectors, in a plurality of memory pages of a memory.

Abstract: Apparatus and methods are provided for calculating soft information in a multi-level modulation scheme using one or more nearest neighbors. The nearest neighbors correspond to signal points in a signal constellation set nearest to the value of a received signal. The nearest neighbors of a received signal can be found by using a second symbol-to-signal point mapping for the signal constellation set that is different from the mapping actually used by the signal modulator. The second symbol mapping can be used to simplify the discover of nearest neighbors. Once the nearest neighbors are found in the second symbol mapping, the nearest symbols can be translated back into the actual symbol mapping using, for example, table lookup. The nearest neighbors in the actual symbol mapping can then be used to compute soft information in the form of, for example, log-likelihood ratios (LLRs).

Abstract: Methods, systems and computer program products for performing hybrid defect detection are disclosed. A hybrid defect detection mechanism may be used to detect various classes of defects (e.g., long and shallow defects, and short and deep defects) while reducing the probability of a miss or false alarm. In some implementations, the hybrid defect detection mechanism may utilize a defect detector that includes one or more defect sub-detectors. Each defect sub-detector may be associated with an individual threshold and sliding window length to enhance the hybrid defect detection process that maximizes the detection of a specific type or class of defects.

Abstract: A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.

Abstract: In a multi-level memory cell, when data to be programmed arrives, the cell is programmed to the lowest-charge state in which any bit position that is being programmed or has already been programmed has the correct value, regardless of the value in that state of any bit position that has not yet been programmed and is not being programmed. The programming of other bit positions based on subsequently arriving data should not then require a transition to an impermissible lower energy state. Although this may result in a transient condition in which some bits have the wrong value, by the time programming is complete, all bits would be expected to have the correct value. A cell may contain any number of bits equal to or greater than two, and programming may be performed cyclically (e.g., from LSB to MSB), anticyclically (e.g., from MSB to LSB), or in any random order.

Abstract: Flash memory stored data modification is described. In embodiments, a flash memory system includes flash memory and a memory controller that manages data write and erase operations to the flash memory. The flash memory includes a first flash memory region of single-write flash memory cells that are each configured for a data write operation and a corresponding erase operation before a subsequent data write operation. The flash memory also includes a second flash memory region of multiple-write flash memory cells that are each configured for multiple data write operations before an erase operation.

Abstract: The present disclosure includes apparatus, systems and techniques relating to pipelined processing. In some implementations, a method performed by a data processing device includes storing data in a memory module. The method includes processing the stored data in accordance with a compression algorithm to produce processed data. Processing the stored data includes pipelined processing of a defined number of symbols of the stored data in parallel, and discarding results of the pipelined processing that are rendered invalid by other results of the pipelined processing. Additionally, the method includes outputting the processed data.