Patents by Inventor Xueshi Yang

Xueshi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for encoding data to meet an output constraint
    Patent number: 8418031
    Abstract: In a method of encoding data, a data block is received; transformed, error-corrected encoded data blocks based on the received data block are generated and one is selected based on a constraint; and the selected data block is transmitted. The method may include adding, to the received data block, pivot data corresponding to different transformations. In an apparatus, an encoded data generator is configured to generate different encoded data block candidates based on a received data block, and a selector is configured to select one of the candidates to output as encoded data based on a constraint. The encoded data generator may include a transformer configured to apply one or more transformations to the received data block, and an error correction code (ECC) encoder configured to apply error correction to the received data block. The encoded data generator and the selector may be included in a transmitter.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: April 9, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems
    Patent number: 8407570
    Abstract: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: March 26, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Monitoring memory
    Patent number: 8407559
    Abstract: Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: March 26, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu, Pantas Sutardja
  • Accessing memory using fractional reference voltages
    Patent number: 8406048
    Abstract: Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: March 26, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu
  • Systems and methods for compressing data in non-volatile semiconductor memory drives
    Patent number: 8407562
    Abstract: A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: March 26, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Gregory Burd, Xueshi Yang
  • Error correction coding with nuisance data
    Patent number: 8402351
    Abstract: The disclosure provides a method that includes receiving a data sector of a plurality of data tiles, wherein each of the plurality of data tiles includes either nuisance data or user data, decoding the received data sector, using an error correction code, to generate a decoded data sector, and determining an error in the decoded data sector. The method further includes identifying, in response to determining the error, at least one data tile from a first plurality of data tiles, such that each of the identified at least one data tiles potentially includes nuisance data, and generating a modified data sector from the received data sector, by correcting at least one of the at least one data tiles in the received data sector.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: March 19, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Methods and apparatus for providing multilevel coset coding and probabilistic error correction
    Patent number: 8402345
    Abstract: Systems and methods are provided for performing multilevel coset coding and probabilistic error correction. Multiple bit data is encoded in a memory by combining one of the bit positions of multiple data values and encoding the combination to form a codeword. A data point containing a bit error is determined by decoding a codeword associated with one of the bit positions. A first coset corresponding to a data point with the error is determined where the coset includes labels representing non-adjacent analog signal levels. Labels in a second coset that includes mutually exclusive labels from the first coset are analyzed to select a label representing a signal level that is closest in proximity to the signal level represented by the data point containing the bit error than the other labels in the second coset. The data point error is corrected by replacing the data point with the selected label.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: March 19, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Method and apparatus for processing nuisance data
    Patent number: 8397139
    Abstract: A memory device having a plurality of nonvolatile memory cells for storing stored data where the stored data includes user stored data and nuisance stored data. A memory controller includes a transmitter for transmitting write data for storage as the stored data in the memory. The transmitter includes a selector for selection of user write data for storage as the user stored data in the memory and for selection of nuisance write data for storage as the nuisance stored data in the memory. The memory controller includes a receiver for receiving the stored data from the memory as read data where the read data includes the user stored data and the nuisance stored data. The receiver includes a Hamming weight detector for detecting the Hamming weights of read data received from the memory for distinguishing user stored data from nuisance stored data.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 12, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Systems and methods for optimizing a product code structure
    Patent number: 8392790
    Abstract: Systems and methods for jointly optimizing various parameters of an error-correction code (e.g., a product code or other multi-dimensional code) are provided. In certain embodiments, joint optimization of coverage assignments, configuration assignments, rate assignments, and/or user data length assignments of an error-correction code is performed so as to achieve desired error-protection performance at minimized implementation complexity. In certain embodiments, coverage assignments of an error-correction code are optimized to achieve a desired performance level with minimized implementation complexity.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 5, 2013
    Assignee: Marvell International Ltd.
    Inventors: Nedeljko Varnica, Xueshi Yang, Zining Wu
  • Group based read reference voltage management in flash memory
    Patent number: 8363478
    Abstract: Apparatuses, methods, and other embodiments associated with group based read reference voltage management in flash memory are described. According to one embodiment, an apparatus includes an interval logic configured to create a finite set of timer intervals, a partition logic configured to selectively assign a Vref value to a set of flash memory cells as a function of a given timer interval during which the set of flash memory cells are programmed, and an adaptation logic configured to selectively adapt a given Vref value associated with a flash memory cell upon determining that the flash memory cell has been read.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Method and apparatus for calibrating a read/write channel in a memory arrangement
    Patent number: 8363501
    Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: Aditya Ramamoorthy, Gregory Burd, Xueshi Yang
  • Write pre-compensation for nonvolatile memory
    Patent number: 8358541
    Abstract: A system including a programming module and an interference module. The programming module is configured to determine a programming value to which a state of a target cell is to be programmed, wherein the programming value is determined based on states of one or more cells near the target cell. The interference module is configured to generate interference values based on (i) the state of the target cell and (ii) the states of the one or more cells near the target cell. The programming module is further configured to determine the programming value based on at least one of the interference values selected according to (i) the state of the target cell and (ii) the states of the one or more cells near the target cell.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: January 22, 2013
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Xueshi Yang, Pantas Sutardja
  • Adapting read reference voltage in flash memory device
    Patent number: 8351258
    Abstract: One example apparatus includes an adaptation logic configured to determine a reference voltage adaptation for a flash memory device as a function of a current reference voltage in use by the flash memory device and a difference of bit error types experienced by the flash memory device. In one embodiment, the difference of bit error types compares a number of zero to one bit errors to a number of one to zero bit errors. In one embodiment, the adaptation logic is further configured to determine a reference voltage adaptation that will shift the reference voltage towards a threshold voltage (Vth) distribution associated with a zero value by an amount that is proportional to the difference of bit errors.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: January 8, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Non-volatile memory devices having uniform error distributions among pages
    Patent number: 8345477
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described systems, for example, includes a non-volatile memory structure that includes memory cells configured to store information based on four or more charge levels associated with four or more states respectively. The four or more states can be indicative of information that includes first bit information in a first bit position and second bit information in a second bit position. The described system includes a controller configured to use at least one of four or more programming voltages associated with the four or more states, respectively, to affect a charge of a memory cell. The programming voltages can be selected to reduce differences among bit error rates of individual bit positions in a state determined by reading a charge of a memory cell.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: January 1, 2013
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Adaptive systems and methods for storing and retrieving data to and from memory cells
    Patent number: 8347187
    Abstract: Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 1, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu
  • Compression based wear leveling for non-volatile memory
    Patent number: 8347023
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. Systems and techniques can include obtaining information to store in a non-volatile memory, the information including a data segment, compressing data within the data segment, including pad data in one or more portions of the data segment based on a compression result attained by the compression, and writing data of the data segment.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: January 1, 2013
    Assignee: Marvell World Trade Ltd.
    Inventor: Xueshi Yang
  • SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION
    Publication number: 20120331368
    Abstract: A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Inventors: Xueshi YANG, Zining WU, Seo-How LOW
  • Sequence detection for flash memory with inter-cell interference
    Patent number: 8339874
    Abstract: A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 25, 2012
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu
  • Hybrid defect detection for recording channels
    Patent number: 8339720
    Abstract: Methods, systems and computer program products for performing hybrid defect detection are disclosed. A hybrid defect detection mechanism may be used to detect various classes of defects (e.g., long and shallow defects, and short and deep defects) while reducing the probability of a miss or false alarm. In some implementations, the hybrid defect detection mechanism may utilize defect detectors to each receive signal samples and apply a different set of parameters indicating a different respective window to the signal samples. Each defect detector may generate a corresponding output based on a count of signal samples within the corresponding window that are associated with abnormal signal quality.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 25, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Yu-Yao Chang, Michael Madden, Zining Wu
  • Determining threshold voltage distribution in flash memory
    Patent number: 8331169
    Abstract: Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 11, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Zining Wu, Gregory Burd