Abstract: High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.

Abstract: A display baseplate includes a display region and a peripheral region, and the display baseplate includes: a substrate, and a gate line driving circuit, a plurality of signal lines, and a gate line provided on one side of the substrate, the gate line driving circuit and the plurality of signal lines all being located in the peripheral region, and the gate line being located in the display region. The gate line driving circuit is respectively connected to the plurality of signal lines and the gate line, and includes a plurality of stages of driving units that are cascaded to each other, each driving unit includes a first element group, and the first element group includes at least one first electronic element. The plurality of signal lines are arranged in a first direction, the first direction is an extending direction of the gate line.

Abstract: A color film substrate, a display substrate and a display apparatus are provided in embodiments of the present disclosure. The color film substrate includes a substrate base plate and a black matrix layer. There are an irregular-shaped active area and a peripheral region surrounding the irregular-shaped active area on the substrate base plate. The irregular active area includes a plurality of first pixels and at least one second pixel, and the second pixel is closer to the peripheral region relative to the first pixels, and a shape of a boundary line of each second pixel close to the peripheral region is the same as a shape of a boundary line of the peripheral region. The black matrix layer includes a plurality of shielding structures, at least one of the plurality of shielding structures shields second pixel in a single-domain manner or at its circumference to form an opening region.

Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic

Abstract: Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.

Abstract: A light emitting module includes a carrier, a light emitting element, a reflection layer, and a fluorescent layer. The light emitting element is disposed on the carrier. The reflection layer is disposed on the carrier and surrounds the light emitting element. The fluorescent layer covers at least part of the light emitting element. The disadvantages of over broad light emitting angle and low illuminance may be solved. Comparing with the related art, the present disclosure achieves an object of increasing the illuminance by at least 10%.

Abstract: Disclosed is a display panel including: first spacer on the array substrate, an orthographic projection of the first spacer on the array substrate being a first pattern extending along a first direction; a second spacer on the counter substrate, an orthographic projection of the second spacer on the array substrate being a second pattern extending along a second direction; at least two third spacers, orthographic projections of which on the array substrate being respectively on two sides of the first pattern along the first direction; at least two fourth spacers, orthographic projections of which on the array substrate being respectively on two sides of the second pattern along the second direction; one of the third spacer and the fourth spacer is on the array substrate, and the other is on the counter substrate.

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

Abstract: A semiconductor component is provided in the form of an enhancement mode high-electron-mobility transistor having an n-i-p semiconductor junction epitaxial structure. The semiconductor component includes: a channel layer and a barrier layer formed on the channel layer. A two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the barrier layer. A gate electrode is disposed on the barrier layer. A semiconductor junction structure is disposed and sandwiched between the gate electrode and the barrier layer. The semiconductor junction structure includes a first region doped with a first dopant and in direct contact with the gate electrode, a second region doped with a second dopant different from the first dopant, and a third region being unintentionally doped and sandwiched between the first region and the second region. The semiconductor junction structure depletes a portion of the 2DEG thereunder.

Abstract: A vitrification device for gametes or embryos, wherein, the vitrification straw comprises: a loading rod, wherein the loading rod is a metal rod; a loading strip, wherein, the loading strip is connected with one end of the loading rod. According to the present invention, the loading rod is arranged as metal rod, which avoids embrittlement fracture caused by sudden temperature change when the loading rod is taken out of liquid nitrogen, moreover, the ice crystals that form on gametes or embryos when the loading rod floats out of the surface of liquid nitrogen, affecting the safety of gametes or embryos, the metal material used by this invention can increase the weight of the loading rod, preventing it from floating up in the liquid nitrogen, hence improve safety of gametes or embryos.

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

Abstract: A visual examining and training device includes a wearing unit that is suitable for wearing on a head of a user, that is configured to be disposed in front of the eyes of the user, and that has a main housing, and two lens adjusting units spacedly disposed in the main housing and each of which includes a lens carrier having a tubular member defining an inner space, a rotary lens holder assembly disposed in the inner space, two prisms coaxially disposed in the rotary lens holder assembly, a focal length adjusting lens disposed in the inner space spaced apart from the prisms, and a drive mechanism connected to the rotary lens holder assembly for driving the same together with the prisms to rotate. A control unit is signally connected to the drive mechanisms of the lens adjusting units for controlling operation of the same.

Abstract: A vitrification device for gametes or embryos, wherein, the vitrification straw comprises: a loading rod, wherein the loading rod is a metal rod; a loading strip, wherein, the loading strip is connected with one end of the loading rod. According to the present invention, the loading rod is arranged as metal rod, which avoids embrittlement fracture caused by sudden temperature change when the loading rod is taken out of liquid nitrogen, moreover, the ice crystals that form on gametes or embryos when the loading rod floats out of the surface of liquid nitrogen, affecting the safety of gametes or embryos, the metal material used by this invention can increase the weight of the loading rod, preventing it from floating up in the liquid nitrogen, hence improve safety of gametes or embryos.

Abstract: A conductive polymeric composition includes, based on a total weight of the conductive polymeric composition, 0.1 wt % to 10 wt % of carbon nanotubes, 0.2 wt % to 4 wt % of a first component, 0.1 wt % to 4 wt % of a second component made by esterification of a C16-C30 fatty acid with a polyol compound, and the balance being a polymeric component. When the first component is a first polymer obtained from polycondensation of an aromatic diacid compound and an aliphatic glycol compound, the polymeric component is a polyester. When the first component is a second polymer obtained from polycondensation of a lactam compound, a diamine compound and a dicarboxylic acid compound, the polymeric component is a polyamide.

Abstract: Disclosed is a display panel including: first spacer on the array substrate, an orthographic projection of the first spacer on the array substrate being a first pattern extending along a first direction; a second spacer on the counter substrate, an orthographic projection of the second spacer on the array substrate being a second pattern extending along a second direction; at least two third spacers, orthographic projections of which on the array substrate being respectively on two sides of the first pattern along the first direction; at least two fourth spacers, orthographic projections of which on the array substrate being respectively on two sides of the second pattern along the second direction; one of the third spacer and the fourth spacer is on the array substrate, and the other is on the counter substrate.

Abstract: The disclosure discloses an algebraic decoding method and a decoder for a (n, n(n?1), n?1) permutation group code in a communication modulation system. The basic principle of the decoding method is: assuming that two code elements p(r1)=s1 and p(r2)=s2 can be correctly detected in a received real vector with a length of n, including their element values s1, s2 and position indices r1, r2 in the vector, an intermediate parameter w is determined by solving an equation (r1?r2)w=(s1?s2)(mod n); and each code element is calculated by w according to p(i)=(s1+(n?r1+i)w)(mod n), i=1, 2, . . . , n. The decoder is mainly composed of multiple n-dimensional registers, a w calculator, n code element calculators, and a code element buffer. In the disclosure, in a case where a receiver only correctly detects two code elements in a transmitted codeword with a length of n, the codeword can be correctly decoded by using the received information of the two code elements.

Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic