Patents by Inventor Ya Yu

Ya Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11238199
    Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 1, 2022
    Assignee: Xilinx, Inc.
    Inventors: Alexandre Isoard, Lin-Ya Yu, Hem C. Neema
  • Publication number: 20210359123
    Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Ya-Yu YANG, Shang-Ju TU, Tsung-Cheng CHANG, Chia-Cheng LIU
  • Patent number: 11158142
    Abstract: A method for tire force reserve estimation is applicable to a vehicle. In the method, vehicle motion information including the longitudinal acceleration, the lateral acceleration, the change of the tire rotation angle at different times, the change of the yaw at different times, the steering angle of the steering tires, etc. is continuously detected, for estimating the current normal force, the current longitudinal force and the current lateral force of each of the tires. Finally, the current normal force, the current longitudinal force, the current lateral force and the coefficient of friction of the road relative to the tires are applied to estimate the longitudinal tire force reserve and the lateral tire force reserve.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 26, 2021
    Assignee: HUA-CHUANG AUTOMOBILE INFORMATION TECHNICAL CENTER CO., LTD.
    Inventors: Bo-Chiuan Chen, Ya-Yu You, Yu-Min Lin, Wei-Jie Chen, Yuan-Chun Chen, Di Ku
  • Publication number: 20210272866
    Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya-Yu HSIEH, Chin-Li KAO, Chung-Hsuan TSAI, Chia-Pin CHEN
  • Publication number: 20210253824
    Abstract: A conductive polymeric composition includes, based on a total weight of the conductive polymeric composition, 0.1 wt % to 10 wt % of carbon nanotubes, 0.2 wt % to 4 wt % of a first component, 0.1 wt % to 4 wt % of a second component made by esterification of a C16-C30 fatty acid with a polyol compound, and the balance being a polymeric component. When the first component is a first polymer obtained from polycondensation of an aromatic diacid compound and an aliphatic glycol compound, the polymeric component is a polyester. When the first component is a second polymer obtained from polycondensation of a lactam compound, a diamine compound and a dicarboxylic acid compound, the polymeric component is a polyamide.
    Type: Application
    Filed: December 9, 2020
    Publication date: August 19, 2021
    Inventors: Chih-Hung Kao, Tzu-Chung Lu, Yin-Lin Lee, Chih-Hua Lin, Ya-Yu Huang
  • Patent number: 11094814
    Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 17, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Ya-Yu Yang, Shang-Ju Tu, Tsung-Cheng Chang, Chia-Cheng Liu
  • Patent number: 11049961
    Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 29, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shang-Ju Tu, Chia-Cheng Liu, Tsung-Cheng Chang, Ya-Yu Yang, Yu-Jiun Shen, Jen-Inn Chyi
  • Patent number: 11038738
    Abstract: The present disclosure provides an encoding method and an encoder for a (n, n(n?1), n?1) permutation group code in a communication modulation system, in which 2k k-length binary information sequences are mapped to 2k n-length permutation codeword signal points in a n-dimensional modulation constellation ?n. The constellation ?n with the coset characteristics is formed by selecting 2k n-length permutation codewords from n(n?1) permutation codewords of a code set Pn,xi of the (n, n(n?1), n?1) permutation group code based on coset partition. The constellation ?n is a coset code in which 2k1 cosets are included and each coset includes 2k2 permutation codewords, where k=k1+k2, and 2k?n(n?1). The present disclosure utilizes the coset characteristics to realize one-to-one correspondence mapping of the binary information sequence set to the permutation code constellation, so that the time complexity of executing the encoder is at most the linear complexity of the code length n.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 15, 2021
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Li Peng, Si Jia Chen, Ying Long Shi, Ya Yu Gao, Bin Dai, Lin Zhang, Kun Liang, Bo Zhou, Zhen Qin
  • Patent number: 11011444
    Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 18, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya-Yu Hsieh, Chin-Li Kao, Chung-Hsuan Tsai, Chia-Pin Chen
  • Publication number: 20210050273
    Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya-Yu HSIEH, Chin-Li KAO, Chung-Hsuan TSAI, Chia-Pin CHEN
  • Publication number: 20200287570
    Abstract: The disclosure discloses an algebraic decoding method and a decoder for a (n, n(n?1), n?1) permutation group code in a communication modulation system. The basic principle of the decoding method is: assuming that two code elements p(r1)=s1 and p(r2)=s2 can be correctly detected in a received real vector with a length of n, including their element values s1, s2 and position indices r1, r2 in the vector, an intermediate parameter w is determined by solving an equation (r1?r2)w=(s1?s2)(mod n); and each code element is calculated by w according to p(i)=(s1+(n?r1+i)w)(mod n), i=1, 2, . . . , n. The decoder is mainly composed of multiple n-dimensional registers, a w calculator, n code element calculators, and a code element buffer. In the disclosure, in a case where a receiver only correctly detects two code elements in a transmitted codeword with a length of n, the codeword can be correctly decoded by using the received information of the two code elements.
    Type: Application
    Filed: December 27, 2019
    Publication date: September 10, 2020
    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Li Peng, Si Jia Chen, Ying Long Shi, Ya Yu Gao, Bin Dai, Lin Zhang, Kun Liang, Bo Zhou
  • Publication number: 20200287774
    Abstract: The present disclosure provides an encoding method and an encoder for a (n, n(n?1), n?1) permutation group code in a communication modulation system, in which 2k k-length binary information sequences are mapped to 2k n-length permutation codeword signal points in a n-dimensional modulation constellation ?n. The constellation ?n with the coset characteristics is formed by selecting 2k n-length permutation codewords from n(n?1) permutation codewords of a code set Pn,xi of the (n, n(n?1), n?1) permutation group code based on coset partition. The constellation ?n is a coset code in which 2k1 cosets are included and each coset includes 2k2 permutation codewords, where k=k1+k2, and 2k?n(n?1). The present disclosure utilizes the coset characteristics to realize one-to-one correspondence mapping of the binary information sequence set to the permutation code constellation, so that the time complexity of executing the encoder is at most the linear complexity of the code length n.
    Type: Application
    Filed: December 27, 2019
    Publication date: September 10, 2020
    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Li Peng, Si Jia Chen, Ying Long Shi, Ya Yu Gao, Bin Dai, Lin Zhang, Kun Liang, Bo Zhou, Zhen Qin
  • Patent number: 10734509
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Epistar Corporation
    Inventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
  • Publication number: 20200151970
    Abstract: A method for tire force reserve estimation is applicable to a vehicle. In the method, vehicle motion information including the longitudinal acceleration, the lateral acceleration, the change of the tire rotation angle at different times, the change of the yaw at different times, the steering angle of the steering tires, etc. is continuously detected, for estimating the current normal force, the current longitudinal force and the current lateral force of each of the tires. Finally, the current normal force, the current longitudinal force, the current lateral force and the coefficient of friction of the road relative to the tires are applied to estimate the longitudinal tire force reserve and the lateral tire force reserve.
    Type: Application
    Filed: December 7, 2018
    Publication date: May 14, 2020
    Inventors: Bo-Chiuan Chen, Ya-Yu You, Yu-Min Lin, Wei-Jie Chen, Yuan-Chun Chen, Di Ku
  • Patent number: 10631383
    Abstract: An illuminant module includes a first illuminant unit, a second illuminant unit, a first phosphor layer, and a second phosphor layer. The first illuminant unit includes one or more first LED dice and a current regulator electrically connected to the LED dice in series. The second illuminant unit includes one or more second LED dice. The first phosphor layer at least covers the first LED dice, wherein first phosphor layer and the first LED dice collectively provide an emission having a first color temperature. The second phosphor layer at least covers the second LED dice, wherein second phosphor layer and the second LED dice collectively provide an emission having a second color temperature, the current regulator is configured to adjust currents flowing to the first illuminant unit and the second illuminant unit for changing luminous flux of emissions emitted from the first illuminant unit and the second illuminant unit.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 21, 2020
    Assignee: PROLIGHT OPTO TECHNOLOGY CORPORATION
    Inventors: Chen-Lun Hsing Chen, Jung-Hao Hung, Ya-Yu Hung, Cheng-Tsan Tang
  • Publication number: 20200034356
    Abstract: A method, an apparatus, a device and a storage medium for implementing an application based on a blockchain network are provided. The method includes: interacting a basic operation with a user via a blockchain platform access interface carried by a locally configured lightweight node; interacting data of the basic operation with a basic chain node in the blockchain network through data of a basic chain deployed in the lightweight node; interacting an application operation with the user through a locally installed application client; and interacting data of the application operation with a node of an application parallel chain corresponding to the application through data of the application parallel chain deployed in the lightweight node.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 30, 2020
    Inventor: Ya'nan YU
  • Publication number: 20200006543
    Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Shang-Ju TU, Chia-Cheng LIU, Tsung-Cheng CHANG, Ya-Yu YANG, Yu-Jiun SHEN, Jen-Inn CHYI
  • Patent number: 10481426
    Abstract: The present disclosure relates to a method for manufacturing a color filter substrate, a color substrate and a display panel in the field of display technology. The method includes: forming a color resistance layer on a basal substrate; forming a conversion layer on the basal substrate with the color resistance layer, wherein the thickness of the conversion layer is greater than the thickness of the color resistance layer and the conversion layer is convertible in color under the irradiation of preset light rays; and irradiating the conversion layer with the preset light rays so that the conversion layer is converted to a two-layer structure consisting of a black matrix (BM) pattern and a transparent over cover, wherein the BM pattern is disposed at the side of the conversion layer close to the basal substrate.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: November 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventors: Rui Yin, Sang Man Yuk, Jian Ma, Ya Yu, Guoqiang Zhong
  • Publication number: 20190341479
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: SHANG JU TU, YA YU YANG, CHIA CHENG LIU, TSUNG CHENG CHANG
  • Patent number: 10396191
    Abstract: A semiconductor device, including: a channel layer formed on a substrate; a top barrier layer formed on the channel layer, wherein a first heterojunction is formed between the channel layer and the top barrier layer so that a first two-dimensional electron gas is generated in the channel layer; a buffer structure formed between the substrate and the channel layer; a back barrier layer formed between the buffer structure and the channel layer, wherein a second heterojunction is formed between the buffer structure and the back barrier layer so that a second two-dimensional electron gas is generated in the buffer structure; and a source electrode, a drain electrode, and a gate electrode formed on the top barrier layer, respectively; wherein a sheet carrier density of the second two-dimensional electron gas is less than 8E+10 cm?2.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 27, 2019
    Assignee: Epistar Corporation
    Inventors: Ya-Yu Yang, Chia-Cheng Lui, Shang-Ju Tu