Abstract: A hybrid MOS-PCM IC switch utilizes both MOS transistors and groups of parallel-connected Phase-Change Material (PCM) cells to control signal transmissions. The MOS transistors are separated by PCM cell groups, and the PCM cells are configured to generate similar COFF or lower values as the MOS transistors, whereby the hybrid switch is both smaller and exhibits lower FOM than standard CMOS SOI switches. When switched into an open (OFF/high-resistance) state, both the PCM cells and MOS transistors function to distribute high VBSR voltages, and the MOS transistors prevent unintended phase changes (ON/OFF switching) of the PCM cells by preventing exponential current flow. In the closed (ON/conducting) state, the PCM cells facilitate lower total RON, whereby the hybrid CMOS SOI switch achieves improved FOM. The MOS transistors may also function as drivers during programming (switching) of direct-heating-type PCM cells.

Abstract: A CMOS gas sensor that uses MTJ elements to capture/store gas concentration level data at high temperatures for later readout at low temperatures. Each MTJ element includes a storage layer whose magnetic orientation is switchable between parallel and anti-parallel directions relative to a fixed reference when heated above the storage layer's blocking temperature, whereby the MTJ element is switchable between low and high resistance states. During operation, reaction heat generated by a gas sensing element raises the MTJ element's temperature above the blocking temperature when ambient target gas exceeds a minimum concentration level, whereby an applied magnetic biasing force causes the storage layer's magnetic orientation to switch relative to the fixed reference, whereby the MTJ element captures measured concentration level data for later readout.

Abstract: A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

Abstract: A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon.

Abstract: Gas sensing using MTJ elements to capture/store gas concentration level data for readout at room temperature. In one embodiment, during reset the MTJ elements are heated above blocking temperatures of their storage layers while applying a first magnetic biasing force to set initial magnetic orientations. During gas sensing, reaction heat from a gas sensing element combines with control heat to raise each MTJ element's temperature from a work point temperature above its blocking temperature only when the target gas exceeds an associated concentration level, whereby a second magnetic biasing force causes the magnetic orientation to switch directions. During readout, read currents are measured to determine the MTJ elements' final resistance states, which indicate their switched/non-switched states, and the resistance states are correlated with stored data to determine the measured gas concentration level. The MTJ elements are cooled after reset and gas sensing to facilitate accurate CDS readout data.

Abstract: A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

Abstract: A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial l

Abstract: A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Abstract: A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial l

Abstract: Gas sensing using MTJ elements to capture/store gas concentration level data for readout at room temperature. In one embodiment, during reset the MTJ elements are heated above blocking temperatures of their storage layers while applying a first magnetic biasing force to set initial magnetic orientations. During gas sensing, reaction heat from a gas sensing element combines with control heat to raise each MTJ element's temperature from a work point temperature above its blocking temperature only when the target gas exceeds an associated concentration level, whereby a second magnetic biasing force causes the magnetic orientation to switch directions. During readout, read currents are measured to determine the MTJ elements' final resistance states, which indicate their switched/non-switched states, and the resistance states are correlated with stored data to determine the measured gas concentration level. The MTJ elements are cooled after reset and gas sensing to facilitate accurate CDS readout data.

Abstract: A CMOS gas sensor that uses MTJ elements to capture/store gas concentration level data at high temperatures for later readout at low temperatures. Each MTJ element includes a storage layer whose magnetic orientation is switchable between parallel and anti-parallel directions relative to a fixed reference when heated above the storage layer's blocking temperature, whereby the MTJ element is switchable between low and high resistance states. During operation, reaction heat generated by a gas sensing element raises the MTJ element's temperature above the blocking temperature when ambient target gas exceeds a minimum concentration level, whereby an applied magnetic biasing force causes the storage layer's magnetic orientation to switch relative to the fixed reference, whereby the MTJ element captures measured concentration level data for later readout.

Abstract: An electronic device is proposed. The electronic device comprises: at least one electronic component formed in a chip of semiconductor material; at least one radioisotope power source unit comprising a radioactive material. The at least one radioisotope power source unit is embedded in the chip of semiconductor material together with the at least one electronic component. Moreover, the at least one radioisotope power source unit is arranged for providing electric power to said at least one electronic component by absorbing particles emitted by said radioactive material comprised in the least one radioisotope power source unit.

Abstract: A two-terminal, single-poly floating gate memristor includes parallel-connected, asymmetrical readout and injection transistors having a shared floating gate structure, and a diode connected to drain terminals of the asymmetrical transistors. The injection transistor is configured with relatively high source/drain-to-gate capacitances to facilitate EEPROM-type (floating gate) program/erase operations (e.g., hot carrier injection and band-to-band tunneling of holes), and the readout transistor is configured (e.g., using a threshold voltage implant) to facilitate low-voltage readout operations. The diode is configured to function both as a limiting resistor that prevents over-erase during high-voltage erase operations, and also to prevent sneak (leakage) currents during low-voltage readout operations. The diode is implemented using either p-n junction or Schottky diode configurations formed on bulk silicon, or a lateral diode configurations disclosed for SOI substrates.

Abstract: An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.

Abstract: A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Abstract: A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures.

Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e.

Abstract: A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures.

Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e.

Abstract: A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature.