Patents by Inventor Yakov Roizin
Yakov Roizin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130051150Abstract: A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell's channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams.Type: ApplicationFiled: February 2, 2012Publication date: February 28, 2013Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Avi Strum
-
Patent number: 8378407Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.Type: GrantFiled: March 2, 2010Date of Patent: February 19, 2013Assignee: Tower Semiconductor, Ltd.Inventors: Mikalai Audzeyeu, Yuriy Makarevich, Siarhei Shvedau, Anatoly Belous, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
-
Patent number: 8344468Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes respectively formed in portions of a planar semiconductor material (e.g., polycrystalline or crystalline silicon) layer that is entirely disposed on an insulating material (e.g., SiO2) layer utilizing, e.g., STI or SOI techniques. Each light-sensitive diode includes parallel elongated doped regions respectively formed by P+ and N+ dopant extending entirely through the semiconductor layer material and separated by an intervening elongated intrinsic (native) region. The light-sensitive diodes are connected in series by patterned conductive (e.g., metal film) structures. Optional bypass diodes are formed next to each lateral P-I-N light-sensitive diodes. Optional trenches are defined between adjacent light-sensitive diodes.Type: GrantFiled: May 18, 2011Date of Patent: January 1, 2013Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay
-
Patent number: 8344440Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.Type: GrantFiled: January 21, 2011Date of Patent: January 1, 2013Assignee: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Micha Gutman, Yakov Roizin
-
Publication number: 20120292675Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes respectively formed in portions of a planar semiconductor material (e.g., polycrystalline or crystalline silicon) layer that is entirely disposed on an insulating material (e.g., SiO2) layer utilizing, e.g., STI or SOI techniques. Each light-sensitive diode includes parallel elongated doped regions respectively formed by P+ and N+ dopant extending entirely through the semiconductor layer material and separated by an intervening elongated intrinsic (native) region. The light-sensitive diodes are connected in series by patterned conductive (e.g., metal film) structures. Optional bypass diodes are formed next to each lateral P-I-N light-sensitive diodes. Optional trenches are defined between adjacent light-sensitive diodes.Type: ApplicationFiled: May 18, 2011Publication date: November 22, 2012Applicant: TOWER SEMICONDUCTOR LTD.Inventors: YAKOV ROIZIN, EVGENY PIKHAY
-
Publication number: 20110121379Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.Type: ApplicationFiled: January 21, 2011Publication date: May 26, 2011Applicant: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Micha Gutman, Yakov Roizin
-
Patent number: 7948020Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: GrantFiled: March 23, 2010Date of Patent: May 24, 2011Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Ishai Naveh
-
Patent number: 7859043Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: GrantFiled: March 5, 2009Date of Patent: December 28, 2010Assignee: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Yakov Roizin
-
Patent number: 7800156Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: GrantFiled: February 25, 2008Date of Patent: September 21, 2010Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Ishai Naveh
-
Patent number: 7795087Abstract: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.Type: GrantFiled: September 10, 2008Date of Patent: September 14, 2010Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Yossi Netzer, Ira Naot, Myriam Buchbinder, Avi Ben-Guigui
-
Publication number: 20100188901Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: ApplicationFiled: March 23, 2010Publication date: July 29, 2010Applicant: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Yakov Roizin
-
Patent number: 7754564Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: GrantFiled: March 12, 2008Date of Patent: July 13, 2010Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Assaf Lahav, Ira Naot, Yakov Roizin
-
Patent number: 7754559Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.Type: GrantFiled: March 19, 2008Date of Patent: July 13, 2010Assignee: Tower Semiconductor Ltd.Inventors: Efraim Aloni, Yakov Roizin, Alexey Heiman, Michael Lisiansky, Amos Fenigstein, Myriam Buchbinder
-
Publication number: 20100172184Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: ApplicationFiled: March 23, 2010Publication date: July 8, 2010Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Ishai Naveh
-
Publication number: 20100157669Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: Tower Semiconductor Ltd.Inventors: Mikalai Audzeyeu, Yuriy Makarevich, Siarhei Shvedau, Anatoly Belous, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
-
Patent number: 7700994Abstract: An electrically erasable/programmable CMOS logic memory cell for RFID applications and other mobile applications includes a tunneling capacitor, a control capacitor, and a CMOS inverter that share a single floating gate. A two-phase program/erase operation performs an initial Fowler-Nordheim (F-N) injection phase using the capacitors, and then a Band-to-Band Tunneling (BBT) phase using the CMOS inverter. Both the F-N injection and BBT phases are performed using low currents and low voltages (i.e., 5V or less). The tunneling and control capacitors are fabricated in isolated P-wells (IPWs) including both N+ and a P+ regions to enable the use of both positive and negative programming voltages during the F-N and BBT programming/erasing operations.Type: GrantFiled: November 7, 2007Date of Patent: April 20, 2010Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Efraim Aloni, Adi Birman, Daniel Nehmad
-
Patent number: 7679119Abstract: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.Type: GrantFiled: November 7, 2007Date of Patent: March 16, 2010Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Victor Kairys, Erez Sarig, David Zfira
-
Patent number: 7671396Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: GrantFiled: January 4, 2006Date of Patent: March 2, 2010Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Asaf Lahav, Ira Naot, Yakov Roizin
-
Publication number: 20100027346Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: ApplicationFiled: October 20, 2009Publication date: February 4, 2010Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Ishai Naveh
-
Publication number: 20100027347Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed.Type: ApplicationFiled: October 20, 2009Publication date: February 4, 2010Applicant: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Yakov Roizin