Abstract: A display panel includes a pair of substrates, a pixel structure, and a display medium layer disposed between the pair of substrates. The pixel structure is disposed on one of the substrates, and includes first and second sub-pixels. The first sub-pixel includes a first pixel electrode, wherein the first pixel electrode has a first spacing in a first main region and has a second spacing in a first minor region, wherein the second spacing is smaller than the first spacing. The second sub-pixel includes a second pixel electrode, wherein the second pixel electrode has a third spacing in a second main region and has a fourth spacing in a second minor region, wherein the fourth spacing is larger than or equal to the third spacing, and wherein the first spacing is larger than the third spacing.

Abstract: Among other things, one or more systems and techniques for transition time evaluation of a circuit are provided herein. In some embodiments, a comparator is configured to receive a circuit signal from the circuit. The circuit signal is evaluated by the comparator based upon one or more control voltages to create one or more voltage waveforms. In some embodiments, the one or more voltage waveforms have substantially similar slopes. A time converter, such as a time-to-current converter or a time-to-digital converter, is used to evaluate the one or more output waveforms to determine a transition time, such as a rise time or a fall time, of the circuit. In some embodiments, the one or more output waveforms are used to reconstruct a transition waveform representing a waveform of the circuit signal.

Abstract: An active device array substrate includes a substrate, a first pixel electrode, and a first raised pattern. The first pixel electrode is disposed on or above the substrate, and the first pixel electrode includes a first truck electrode, a second truck electrode, and a plurality of first branch electrodes. The first truck electrode and the second truck electrode intersect to form a first node at the intersection of the first truck electrode and the second truck electrode. The first branch electrodes are connected to the first truck electrode and the second truck electrode to form a plurality of first domains, wherein the first branch electrodes are asymmetrical with respect to the second truck electrode. The first raised pattern is disposed at least between the first node and the substrate to form a first raised structure at least at the first node.

Abstract: Provided is a single-stranded nucleic acid aptamer specifically binding to Klebsiella pneumoniae, and a method for detecting Klebsiella pneumoniae by using the same. The aptamer of the present disclosure, and a method, a composition, a kit or a sensor of using the same may be used to specifically detect Klebsiella pneumoniae present in an aqueous environment, foods, and medical samples and also be applied in fields such as sanitary conditions of foods and medical diagnosis.

Abstract: A protective device includes a substrate, an electrode layer, a metal structure, an outer cover and an arc extinguishing structure. The electrode layer is disposed on the substrate. The electrode layer includes at least one gap. The metal structure is disposed on the electrode layer and located above the gap, and the metal structure has a melting temperature lower than a melting temperature of the electrode layer. The outer cover is disposed on the substrate and covers the metal structure and a portion of the electrode layer. The arc extinguishing structure is disposed between the outer cover and the substrate. A protective module is further provided.

Abstract: A pixel driving method is adapted for a liquid crystal display. Each pixel includes a first sub-pixel and a second sub-pixel, in which the first sub-pixel and the second sub-pixel each includes a first display region and a second display region. The pixel driving method includes providing a first voltage to the first displaying region of the first sub-pixel and the second sub-pixel; providing a second voltage to the second displaying region of the first sub-pixel and a third voltage to the second displaying region of the second sub-pixel; and when the provided first voltage is larger than a predetermined voltage, providing the second voltage so that the provided second voltage is smaller than the provided third voltage.

Abstract: Embodiments of mechanisms for cleaning a wafer are provided. A method for cleaning a wafer includes cleaning a wafer by using a wafer scrubber and cleaning the wafer scrubber in a scrubber cleaning module. An agitated cleaning liquid is applied on the wafer scrubber to clean the wafer scrubber. The method also includes cleaning the wafer or a second wafer by the wafer scrubber after the wafer scrubber is cleaned by the agitated cleaning liquid.

Abstract: A pixel structure and a liquid crystal display (LCD) panel having the same are provided. The pixel structure includes a data line, a scan line, at least one active device, a pixel electrode, and a metal line. The active device is electrically connected to the data line and the scan line. The pixel electrode is electrically connected to the active device and has an opening at the edge of the pixel electrode adjacent to at least one of the data line and the scan line. The metal line is located below the pixel electrode. Besides, a portion of the metal line extending to the edge of the pixel electrode is exposed by the opening. The shortest distance between an edge of the opening of the pixel electrode and the metal line is greater than or substantially equal to 3 ?m.

Abstract: A pixel structure including a first active device, a second active device, a first pixel electrode, a second pixel electrode, a third pixel electrode, a coupling electrode, and a capacitance electrode is provided. The first pixel electrode connected to the first active device and defines a first to a fourth liquid crystal alignment domain having different alignment directions. The second pixel electrode is connected to the coupling electrode and defines a fifth to an eighth liquid crystal alignment domain having different alignment directions. The third pixel electrode is connected to the second active device and defines a ninth and a tenth liquid crystal alignment domain. The coupling electrode is connected between the first active device and the second active device and extended to pass through the first, the second, and the third pixel electrodes. The capacitance electrode respectively overlaps parts of the first, the second, and the third pixel electrodes.

Abstract: A pixel structure includes a first conductive layer, a stacked layer, and a third conductive layer. The first conductive layer includes a first gate, a first scan line connected to the first gate, and a capacitor electrode separated from the first scan line. The stacked layer includes a semiconductor layer and a second conductive layer. The second conductive layer includes a data line, a first source connected to the data line, a second source, a first drain, a second drain, a connecting electrode connected to the second source and electrically connected to the first drain, and a coupling electrode connected to the second drain. The third conductive layer includes a first pixel electrode connected to the first drain, a second pixel electrode electrically connected to the connecting electrode, a first extending portion, and a second extending portion.

Abstract: Some embodiments relate to methods and apparatus for mitigating high metal concentrations in photoresist residue and recycling sulfuric acid (H2SO4) in single wafer cleaning tools. In some embodiments, a disclosed single wafer cleaning tool has a processing chamber that houses a semiconductor substrate. A high oxidative treatment unit may apply a high oxidative chemical pre-treatment to the semiconductor substrate to remove a photoresist residue having metal impurities from the semiconductor substrate in a manner that results in a contaminant remainder. A SPM cleaning unit apply a sulfuric-peroxide mixture (SPM) cleaning solution to the semiconductor substrate to remove the contaminant remainder from the semiconductor substrate as an SPM effluent. The SPM effluent is provided to a recycling unit configured to recover sulfuric acid (H2SO4) from the SPM effluent and to provide the recovered H2SO4to the SPM cleaning unit via a feedback conduit.

Abstract: A pixel array substrate with new pixel design and a liquid crystal display panel with the pixel array substrate are provided. The pixel array substrate includes a plurality of data lines, a plurality of scan lines and a plurality of pixels. Each of the pixels comprises a first electrode, a first connecting line, a second electrode and a second connecting line. The first electrode is electrically connected with corresponding data line and scan line through the first connecting line, and having a slit. The second pixel is electrically connected with corresponding data line and scan line through the second connecting line. At least a part of the second connecting line is exposed by the slit of the first electrode.

Abstract: One or more techniques or systems for cleaning wafers during semiconductor fabrication or an associated brush are provided herein. In some embodiments, the brush includes a brush body and one or more inner hole supports within the brush body. For example, a first inner hole support and a second inner hole support define a first inner hole associated with a first size. For another example, a third inner hole support and a fourth inner hole support define a second inner hole associated with a second size different than the first size. In some embodiments, a cleaning solution is applied to a wafer based on a first flow rate at a first brush position and based on a second flow rate at a second brush position. In this manner, a flow field associated with wafer cleaning is provided, thus enhancing cleaning efficiency, for example.

Abstract: A protective device includes a substrate, an electrode layer, a metal structure, an outer cover and an arc extinguishing structure. The electrode layer is disposed on the substrate. The electrode layer includes at least one gap. The metal structure is disposed on the electrode layer and located above the gap, and the metal structure has a melting temperature lower than a melting temperature of the electrode layer. The outer cover is disposed on the substrate and covers the metal structure and a portion of the electrode layer. The arc extinguishing structure is disposed between the outer cover and the substrate. A protective module is further provided.

Abstract: Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example.

Abstract: A display panel includes a pair of substrates, a pixel structure, and a display medium layer disposed between the pair of substrates. The pixel structure is disposed on one of the substrates, and includes first and second sub-pixels. The first sub-pixel includes a first pixel electrode, wherein the first pixel electrode has a first spacing in a first main region and has a second spacing in a first minor region, wherein the second spacing is smaller than the first spacing. The second sub-pixel includes a second pixel electrode, wherein the second pixel electrode has a third spacing in a second main region and has a fourth spacing in a second minor region, wherein the fourth spacing is larger than or equal to the third spacing, and wherein the first spacing is larger than the third spacing.

Abstract: An apparatus comprises a process chamber, and a loadlock connected to the process chamber. The loadlock is configured to have a wafer holder disposed therein. The wafer holder is configured to store a plurality of wafers, and is configured to transport the plurality of wafers away from the loadlock.

Abstract: An energy storage device and a method of manufacturing the same are disclosed. The energy storage device includes a circuit board, a conductive cover disposed above the circuit board, a sealing structure, a metal coating layer, and an electrochemical cell. The sealing structure is disposed between the circuit board and the circumference of the conductive cover such that the circuit board, the conductive cover, and the sealing structure together form a sealed space where the electrochemical cell is disposed. The metal coating layer continuously covers a part of the conductive cover, an exposed portion of the sealing structure, and a part of the circuit board. Therefore, even if the energy storage device needs to be heated during a product assembly, the metal coating layer can keep the sealing structure structurally stable, and the electrolyte of the electrochemical cell will not leak; the whole energy storage device therefore can keeps undamaged.

Abstract: A magnet wire has a conductor and a coating layer. The coated layer is coated around the conductor and has at least one magnetic coating layer; and at least one insulating coating layer. The magnetic coating layer has non-conductive magnetic material. The insulating coating layer and the magnetic coating layer are formed alternately. The alternative structure of the magnetic coating layer and the insulating coating layer prevent precipitation of magnetic material and efficiently offsets the interference between conductors after electricity is supplied, which inhibits occurrence of eddy current and lowers alternative current (AC) resistance.

Abstract: An enameled wire containing a nano-filler includes a metallic wire and at least one layer of insulating coating. At least one layer of the at least one layer of insulating coating includes a nano-filler. The nano-filler is a modified silicon dioxide slurry comprising silicon dioxide, organic solvent and organic silane coupling agent. The nano-filler comprises silicon dioxide modified with an organic silane coupling agent to improve dispersion of the nano-filler and maintain properties of the insulating coating. In addition, material and manufacturing costs of the enameled wire can be lowered.