Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

Abstract: The present disclosure discloses a battery pack that realizes miniaturization and weight reduction by minimizing the number of components of the structure, and that is suitable for pursuing dispersion of external force and structural rigidity using the shape of the structure. The battery pack according to the present disclosure is characterized to include a lower case including both inclined side walls and fixating members facing each other at the both side walls, a battery cartridge disposed between the fixating members in the lower case, and an upper case covering the lower case and the battery cartridge, wherein the battery cartridge contacts the both side walls and the fixating members in the lower case.

Abstract: Provided is a bus bar structure which may be suitable for reducing an occupied area of a printed circuit board (PCB) by removing a fuse from the PCB in an interconnect board (ICB) assembly of a battery pack. According to the present disclosure, the bus bar structure may include: bus bars which face each other and are arranged below the PCB in the ICB assembly of the battery pack; and a fuse case between the bus bars, wherein the fuse case includes a fuse wire therein and is configured to bring the fuse wire into contact with the bus bars via at least one end thereof.

Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).

Abstract: Provided is a battery module including: a battery cell assembly including a plurality of battery cells stacked with one another; end plates configured to cover front and rear portions of the battery cell assembly and to be coupled to the battery cell assembly at a side of each of the end plates; and a fixing holder configured to be mounted to a battery cell assembly at an opposite side of each of the end plates in order to at least partially cover the battery cell assembly, and to protrude from front and rear portions of the end plates.

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

Abstract: A manufacturing method of a triboelectric energy harvester, including the steps of generating an electrification material with a surface of a micro-nano pattern on an electrode and forming a coating electrification layer to support the micro-nano pattern on a surface of the electrification material, is provided.

Abstract: The present disclosure discloses a battery pack suitable for preventing simultaneous separation of both ends of a handle unit from an upper case during transportation of a lower case and the upper case that are laminated sequentially. The battery pack according to the present disclosure includes the lower case and the upper case stacked sequentially to encase a battery module, wherein the upper case includes a housing and a handle unit relatively rotated with respect to the housing to be seated on the housing, and the handle unit has shaft hooks that are penetrated by the rotation supporting shafts of the housing and that are each rotary-coupled to each of the rotation supporting shafts in different angles.

Abstract: The present disclosure discloses a pack case suitable for preventing vibration or deviation of a battery module on a case during an assembly operation, and a battery pack including the same. The pack case according to the present disclosure includes an align unit and a bus bar disposed at an edge on an inner circumferential surface, and a main case having a connection terminal contacting the bus bar on an outer circumferential surface, and the align unit and the bus bar contact a battery module at a periphery of the battery module seated on the inner circumferential surface of the main case.

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

Abstract: Disclosed are a clamping device and a battery module comprising the same, the clamping device being suitable for reducing the number of screw coupling portions of long bolts at a lower plate, a battery stack, and an upper plate, and for securing, in a balanced manner, the battery stack, the lower plate and the upper plate by means of the long bolts. The clamping device according to the present invention comprises: a support; and pressing parts respectively protruded from one end and the other end of the support, wherein the support and the pressing parts define a bent part along the central portion of the outer circumference while forming a band shape, and the pressing parts include locking holes which intersect with the bent portion.

Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

Abstract: Disclosed are a hardware-based selective security apparatus and a security method using the same. The security apparatus according to an embodiment of the present invention includes: a transistor including a source electrode, a drain electrode, and a gate electrode composed of at least two electrodes; and a controller which selectively sets a security level 1 or a security level 2 by controlling a magnitude of a voltage which is applied to the gate electrode. According to the present invention, since there is no necessity of an additional space for a separate chip required by an existing hardware based security method, it is possible to obtain a recoverable hardware based security method which uses spaces usefully and has economic efficiency. Also, a recoverable security level and an irrecoverable security level are selectively applied, so that it is possible to implement an enhanced hardware-based security method.

Abstract: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.

Abstract: The present invention relates to a bio-silica chip comprising a silica-binding protein and a fabrication method thereof, and more particularly to a bio-silica chip in which a fusion protein of a silica-binding protein and a probe protein is immobilized on a chip comprising a silica layer, a fabrication method thereof and a method of using the bio-silica chip to detect interactions with biomaterials. The bio-silica chip will be very useful in biosensors, etc., because the bio-silica chip is advantageous in that it does not cause non-specific protein binding in the detection of protein-DNA, protein-ligand, protein-antibody, protein-peptide, protein-carbohydrate, protein-protein and cell-biomaterial interactions. Also, in the method for fabricating the bio-silica chip, a probe chip can be selectively immobilized on a silica device chip, which is widely used in biosensors, without a chemical surface treatment process.

Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.

Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.