Abstract: The present invention relates to a Field-Effect Transistor (FET) and, more particularly, to a Dielectric-Modulated Field-Effect Transistor (DMFET) and a method of fabricating the same. A DMFET according to an embodiment of the present invention comprises a substrate in which a source and a drain are formed, wherein the source and the drain are spaced apart from each other, a gate formed on a region between the source and the drain, of the substrate, wherein at least part of the gate is spaced apart from the substrate, biomolecules formed below a region spaced apart from the substrate, of the gate, and a linker for combining the gate and the biomolecules.

Abstract: The present invention relates to a non-volatile memory cell and a method of fabricating the same. The non-volatile memory cell according to the present invention comprises a substrate, a first oxide film formed over an active region of the substrate, a source and drain formed within the active region, a charge storage unit formed on the first oxide film, a second oxide film configured to surround the charge storage unit and formed on the first oxide film, and a gate formed to surround the second oxide film. According to the non-volatile memory cell and a cell array including the same in accordance with the present invention, the charge storage unit is fully surrounded by the gate or the gate line, thus a disturbance phenomenon that may occur due to the memory operation of cells formed in other neighboring gate or gate line can be minimized.

Abstract: Discloses are a method for manufacturing a field effect transistor comprising a channel consisting of silicon fins and a silicon body, in which the silicon fins have an orientation different from the silicon body, as well as a transistor structure manufactured thereby.

Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.

Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.

Abstract: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.

Abstract: The present invention relates to a composition for the prevention and the treatment of cardiovascular disease containing extracts of T. nucifera or abietane diterpenoid compound or terpenoid compound isolated from the same as an effective ingredient. T. nucifera extracts or abietane diterpenoid compound or terpenoid compound isolated from the same of the present invention not only shows excellent anti-oxidative activity to LDL but also effectively inhibits ACAT activity. Further, T. nucifera extracts of the present invention reduce blood LDL cholesterol and total cholesterol. Therefore, the composition of the present invention can be effectively used for the prevention and the treatment of cardiovascular diseases including hyperlipidemia and atherosclerosis caused by the LDL oxidation and the synthesis and accumulation of cholesteryl ester.

Abstract: Provided are a phase change memory device that can operate at low power and improve the scale of integration by reducing a contact area between a phase change material and a bottom electrode, and a method for fabricating the same. The phase change memory comprises a current source electrode, a phase change material layer, a plurality of carbon nanotube electrodes, and an insulation layer. The current source electrode supplies external current to a target. The phase change material layer is disposed to face the current source electrode in side direction. The carbon nanotube electrodes are disposed between the current source electrode and the phase change material layer. The insulation layer is formed outside the carbon nanotube electrodes and functions to reduce the loss of heat generated at the carbon nanotube electrodes.

Abstract: Provided are a CMOS image sensor and a method for fabricating the same. A nanopillar is plurally formed at an upper end of a light receiving element.

Abstract: Discloses are a method for manufacturing a field effect transistor comprising a channel consisting of silicon fins and a silicon body, in which the silicon fins have an orientation different from the silicon body, as well as a transistor structure manufactured thereby.

Abstract: Disclosed is a CMOS image sensor, comprising a photodiode formed in a substrate, a floating diffusion region formed in the substrate in a manner such that it is distanced from the photodiode surrounds the photodiode and a transfer gate formed in a manner such that it is distanced from the photodiode and the floating diffusion region and formed in a boundary area between the photodiode and the floating diffusion region, thereby overlapping the photodiode and the floating diffusion region.

Abstract: A transistor including a metal-insulation transition material and a method of manufacturing the same. The transistor including a metal-insulator transition material may include a substrate, a insulation layer formed on the substrate, a source region and a drain region separately formed from each other on the insulation layer, a tunneling barrier layer formed on at least one surface of the source region and the drain region, a metal-insulator transition material layer formed on the tunneling barrier layer and the insulation layer, a dielectric layer stacked on the metal-insulator transition material layer, and a gate electrode layer formed on the dielectric layer.

Abstract: Provided is a flash memory, and more particularly, to a method and structure for erasing flash blocks based on back-bias. The method comprises the steps of forming a flash block on a silicon on insulator (SOI) substrate and forming a body-electrode on back side of the silicon on insulator (SOI) substrate.

Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.

Abstract: The present invention relates to a SON MOSFET and method of manufacturing the same, in which a blister is formed within a silicon substrate, thus improving the disadvantages of a bulk structure and a Silicon-On-Insulator (SOI) structure at the same time. The SON MOSFET according to the present invention comprises isolation insulating films formed at both upper sides of a silicon substrate, a gate insulating film and a gate electrode that are sequentially formed on a surface of the silicon substrate between the isolation insulating films, a source region and a drain region that are formed on the silicon substrate between the gate insulating film and the isolation insulating films, a blister formed within the silicon substrate under the gate insulating film, and a silicon channel, which is surrounded by the blister, the source region and the drain region, within the silicon substrate, wherein the blister is formed of hydrogen or helium ion.

Abstract: The present invention relates to a method of forming a nanogap, a method of manufacturing a nano field effect transistor for a molecular device or a bio-sensor, and a fabrication thereof, and more particularly, to a method of forming a high reproductive nanogap using a thin layer with a molecular size or a size which is similar to that of a molecule and a nano field effect transistor manufactured by the method of forming the nanogap.

Abstract: 0A method for treating or preventing an elevated blood lipid level-related disease in a mammal, which comprises administering thereto an effective amount of rutin, quercetin or a mixture thereof.

Abstract: A method for treating or preventing an elevated blood lipid level-related disease in a mammal, which comprises administering thereto an effective amount of rutin, quercetin or a mixture thereof.

Abstract: The present invention relates to a spice composition comprising 1 to 30 % by weight of garlic, 10 to 50% by weight of onion, 0.2 to 10% by weight of ginger, 5 to 40% by weight of jujube, and 10 to 50% by weight of citrus peel or an extract thereof or 1 to 20% by weight of naringin or hesperidin.

Abstract: A compound of formula (I) treating or preventing an elevated blood lipid level-related disease and inhibiting the activities of acyl-CoA:cholesterol-O-acyltransferase(ACAT) and 3-hydroxy-3-methylglutaryl CoA(HMG-CoA) reductase: wherein, R1 is R5 R6CO group; R2 is H or R6CO group; R3 is H, CH3, R5 or R6CO group; R4 is H, OH, OR5 or R6COO group; R5 is a C2-5 alkyl group substituted with a phenyl group optionally having one or more substituents selected from the group consisting of C1-3 alkyl, OH, Cl and NO2; a C1-5 alkyl group substituted with a naphthyl group optionally having one or more substituents selected from the group consisting of C1-3 alkyl, OH, Cl and NO2; a C10-18 alkyl; or a C10-18 alkenyl group; and R6 is a C10-18 alkenyl group; or an aryl group optionally having one or more substituents selected from the group consisting of C1-3 alkyl, OH, Cl or NO2.