Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

Abstract: Provided are a communication method, a terminal device and a network device. The terminal device receives configuration information sent by a network device, the configuration information being used for indicating one or more conditions for the terminal device to report random access-related information. The terminal device sends a successful handover report that does not contain the random access-related information to the network device in response to a random access of the terminal device not satisfying the one or more conditions for reporting the random access-related information.

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Abstract: The present disclosure provides IL2 proproteins comprising an IL2 moiety that is masked with an IL2R? moiety and a protease-cleavable linker, configured such that the IL2R? moiety is released from the IL2 moiety upon the action of a protease, e.g., at a tumor site. The IL2 proproteins optionally further comprise a targeting moiety, e.g., a targeting moiety that recognizes a tumor-associated antigen and directs the proprotein to a tumor site. The disclosure further provides pharmaceutical compositions comprising the IL2 proproteins, and methods of use of the IL2 proproteins in therapy, as well as nucleic acids encoding the IL2 proproteins, recombinant cells that express the IL2 proproteins and methods of producing the IL2 proproteins.

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Abstract: A feedback control circuit of a pulse-frequency modulation (PFM) converter includes a multiplexer circuit and a detection circuit. The multiplexer circuit is arranged to receive a plurality of candidate peak current values, and output one of the plurality of candidate peak current values as a target peak current value according to a selection control signal, wherein a peak current value of an inductor current pulse of the PFM converter is subject to the target peak current value. The detection circuit is arranged to adaptively adjust the selection control signal according to a pulse interval between two successive inductor current pulses of the PFM converter.

Abstract: A matrix calculation device including a storing unit, a multiply accumulate (MAC) circuit, a pre-fetch circuit, and a control circuit, and an operation method thereof are provided. The storing unit stores a first and second matrixes. The MAC circuit is configured to execute MAC calculation. The pre-fetch circuit pre-fetches at least one column of the first matrix from the storing unit to act as pre-fetch data, pre-fetches at least one row of the second matrix from the storing unit to act as the pre-fetch data, or pre-fetches at least one column of the first matrix and at least one row of the second matrix from the storing unit to act as the pre-fetch data. The control circuit decides whether to perform the MAC calculation on a current column of the first matrix and a current row of the second matrix through the MAC circuit according to the pre-fetch data.

Abstract: A method for preparing dihydromyricetin nanocrystals includes: uniformly dispersing dihydromyricetin in a good solvent to obtain a dihydromyricetin solution; uniformly dispersing a precipitator and a stabilizer in water to obtain a mixed solution, and then adding the dihydromyricetin solution into the mixed solution and mixing uniformly under a stirring condition to obtain a dihydromyricetin nanocrystal solution; and drying the dihydromyricetin nanocrystal solution to obtain the dihydromyricetin nanocrystals. The method for preparing the dihydromyricetin nanocrystals by an anti-solvent method is simple and easy to implement, low in cost, good in nanocrystal stability, small in organic solvent consumption, and safe and environment-friendly in preparation process.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

Abstract: A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

Abstract: The present disclosure provides IL2 proproteins comprising an IL2 moiety that is masked with an IL2R? moiety and a protease-cleavable linker, configured such that the IL2R? moiety is released from the IL2 moiety upon the action of a protease, e.g., at a tumor site. The IL2 proproteins optionally further comprise a targeting moiety, e.g., a targeting moiety that recognizes a tumor-associated antigen and directs the proprotein to a tumor site. The disclosure further provides pharmaceutical compositions comprising the IL2 proproteins, and methods of use of the IL2 proproteins in therapy, as well as nucleic acids encoding the IL2 proproteins, recombinant cells that express the IL2 proproteins and methods of producing the IL2 proproteins.

Abstract: A torque sensor includes a sleeve member configured to be mounted on a center shaft, and a tubular sensor body arranged coaxially with the sleeve member. At least one outer surface of the sleeve member includes one or more magnetostrictive elements. The tubular sensor body includes a bobbin for mounting a sensor coil. An induced current in the sensor coil is detected in response to pedaling by a user. The tubular sensor body includes one or more inclined surfaces inclined with respect to a radial direction of the torque sensor, the one or more inclined surfaces being coupled with the sleeve member or the center shaft.

Abstract: A radio frequency device includes a substrate, an epitaxial structure, a first electrode, a second electrode, a gate structure, a metal bulk, an auxiliary metal bulk, and a metal connection line. The first/second electrode includes a first/second electrode body and first/second electrode fingers. The gate structure includes a sub-gate having parallel portions and vertical portions alternately connected to one another in series to form a serpentine shape. The auxiliary metal bulk is arranged between corresponding adjacent two parallel portions and between a corresponding vertical portion and an end of a corresponding first electrode finger. The metal bulk is arranged between the auxiliary metal bulk and the vertical portion corresponding to the auxiliary metal bulk. The metal connection line connects the metal bulk to the second electrode body and is insulated from the sub-gate. A radio frequency front-end apparatus including the radio frequency device is also disclosed.

Abstract: Provided is a blood collection tube sorting and centrifugal balancing device including a body frame. A vacuum blood collection tube mechanism, a centrifugal balancing tube mechanism, a sorting mechanism, a scanning identification mechanism, a test tube transporting mechanism, and a collection box are arranged on the body frame. The vacuum blood collection tube mechanism and the centrifugal balancing tube mechanism are parallelly arranged on an upper part of the body frame. The scanning identification mechanism is connected to the vacuum blood collection tube mechanism. The sorting mechanism is connected to the vacuum blood collection tube mechanism and the centrifugal balancing tube mechanism at two ends of the sorting mechanism, respectively. The test tube transporting mechanism is connected to the centrifugal balancing tube mechanism. The collection box is disposed in a middle part of the body frame and located directly below the vacuum blood collection tube mechanism.

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A memory device is provided. The memory device includes a semiconductor substrate, a tunneling layer, a floating gate electrode, a dielectric layer, and a control gate electrode. The semiconductor substrate has an active region. The tunneling layer is over the active region of the semiconductor substrate. The floating gate electrode is over the tunneling layer. The floating gate electrode has a first portion and a second portion electrically connected to the first portion. The dielectric layer is over the floating gate electrode. The control gate electrode is over the dielectric layer. The control gate electrode has a first portion interposed between the first and second portions of the floating gate electrode.

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Abstract: Disclosed are small molecule inhibitors of ?v?6 integrin, and methods of using them to treat a number of diseases and conditions.