Abstract: The present disclosure relates to methods and apparatus for determining device information. In one example method, an inference device sends a first request to a service discovery entity. The first request is used to request information about one or more training devices, and the first request includes an algorithm type or an algorithm identifier of a first model requested by the inference device. The inference device receives the information about the one or more training devices from the service discovery entity. The information about the one or more training devices includes capability information. The inference device determines a first training device from the information about the one or more training devices based on a preset condition.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.

Abstract: Lock indicators useable to signal the locked or unlocked state of a lock where the lock indicator is usable with an adjustable rose for accommodating various door thicknesses.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a carbon nanotube structure, a source electrode and a drain electrode. The gate insulating layer is located on the gate electrode. The carbon nanotube structure is located on the gate insulating layer. The source electrode and the drain electrode are arranged at intervals and electrically connected to the carbon nanotube structure respectively. The thin film transistor further includes an interface charge layer, and the interface charge layer is located between the carbon nanotube structure and the gate insulating layer.

Abstract: A graphene heating chip includes a substrate, an insulating layer, a graphene film, and a plurality of electrodes. The substrate has two opposite a first surface and a second surface, and the substrate defines a through hole. The insulating layer is suspended on the substrate. The insulating layer covering the through hole and not in direct contact with the first surface is defined as a window, and a plurality of grooves are formed on the window. The graphene film covers the window, and the graphene film includes a first graphene film portion and a second graphene film portion, and the first graphene film portion and the second graphene film portion are spaced apart from each other. The plurality of electrodes are located on the surface of the insulating layer away from the substrate. The present application also provides a method for calibrating a temperature of the graphene heating chip.

Abstract: A graphene heating chip includes a substrate, an insulating layer, a graphene film, and a plurality of electrodes. The substrate has two opposite a first surface and a second surface, and the substrate defines a through hole. The insulating layer is suspended on the substrate. The insulating layer covering the through hole and not in direct contact with the first surface is defined as a window, and a plurality of grooves are formed on the window. The graphene film covers the window, and the graphene film includes a first graphene film portion and a second graphene film portion, and the first graphene film portion and the second graphene film portion are spaced apart from each other. The plurality of electrodes are located on the surface of the insulating layer away from the substrate. The present application also provides a method for making the graphene heating chip.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

Abstract: The present application provides an inverter. The inverter includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form air gaps, and the air gaps are distributed at both sides of the bottom electrode. The gate electrode is configured to connect with a signal input terminal, the bottom electrode is configured to connect with a signal output terminal.

Abstract: A field effect transistor includes a gate electrode, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer is located on the surface of the gate electrode, and the channel layer is located on the surface of the insulating layer away from the gate electrode. The source electrode and the drain electrode are spaced apart from each on the surface of the channel layer away from the insulating layer. The source electrode and the drain electrode are one-dimensional structures. The present application further provides a method for making the field effect transistor.

Abstract: A field effect transistor includes a gate electrode, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer is located on the surface of the gate electrode, and the channel layer is located on the surface of the insulating layer away from the gate electrode. The source electrode and the drain electrode are spaced apart from each on the surface of the channel layer away from the insulating layer. The source electrode and the drain electrode are one-dimensional structures. The present application further provides a method for making the field effect transistor and a method for measuring an interface resistance of the field effect transistor.

Abstract: A prosthetic heart valve is constructed from a flexible substrate that can be folded from an unfolded configuration to a folded configuration, in which the prosthesis is operable as a prosthetic heart valve. The prosthetic heart valves can be designed as atrioventricular valves (e.g., tricuspid valve, mitral valve) or as semilunar valves (e.g., aortic valve, pulmonary valve).

Abstract: An optical biometer including a light source, a first-stage coupler, a first and a second second-stage coupler, a first and a second optical path difference generator, a first and a second optical component set, a first and a second detection device is disclosed. The first-stage coupler receives an incident light from the light source and emits first and second first-stage lights. The first second-stage coupler receives the first first-stage light and emits first and second second-stage lights. The second second-stage coupler receives the second first-stage light and emits third and fourth second-stage lights. The first/second optical path difference generator generates the first/fourth second-stage light with the first/second optical path difference. The first/second optical component set emits the second/third second-stage light to a first/second position of an eye and receives a first/second reflected light. The first/second detector receives a first/second detection light.

Abstract: The present invention provides modified glucagon-like peptide 1 (GLP1) polypeptides, fusion proteins comprising modified GLP1 polypeptides, and methods of use thereof. In various embodiments of the invention, the fusion proteins are GLP1 receptor agonists that comprise a modified GLP1 fused to a stabilizing domain. In some embodiments, the fusion proteins comprising modified GLP1 are useful for treating or ameliorating a symptom or indication of a disorder such as obesity and diabetes.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1?xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.