Abstract: The present invention discloses an electronic device, including a device housing, a sound apparatus, and a screen. The screen covers the device housing and is provided with a first sound hole at a joint with the device housing. The sound apparatus is disposed in the device housing, and the sound apparatus includes an apparatus housing and an electroacoustic module. The electroacoustic module includes a first diaphragm and a second diaphragm, the apparatus housing is connected to the first diaphragm and the second diaphragm, and the device housing is provided with a second sound hole. When the electroacoustic module is in a first state, the first sound wave formed by the vibration of the first diaphragm and the second sound wave formed by the vibration of the second diaphragm are in opposite phases.

Abstract: An optical biometer includes a light-source module, a light-splitting module, a reference-arm, a sensing-arm and a sensing module. The light-source module emits incident-light. The light-splitting module, disposed corresponding to light-source module, divides the incident-light into reference light and sensing light. The reference-arm, disposed corresponding to light-splitting module, generates a first reflected-light according to the reference light. The sensing-arm, disposed corresponding to the light-splitting module, emits the sensing light to the eye and receives a second reflected-light from the eye. The sensing module generates a sensing result according to the first reflected-light and second reflected-light. In a first mode, the sensing light is emitted to a first position of the eye. In a second mode, the sensing light is emitted to a second position of the eye.

Abstract: An optical detection system integrating tonometer and autorefractor includes first and second optical modules. The first optical module includes a light source, first and second lens sets, a reflector, a first light-splitter and a sensor. The first lens set and reflector are disposed corresponding to light source. The first light-splitter is disposed corresponding to the reflector, second lens set and sensor. The second optical module includes a second light-splitter and first to third optical elements. The incident light emitted by the light source passes through the first lens, reflected by the reflector, passes through the first light-splitter, reflected by the second light-splitter, passes through the first to third optical elements and emitted to an eye. A sensing light from the eye passes through the third to first optical elements, reflected by the second light-splitter and first light-splitter, passes through the second lens set and emitted to the sensor.

Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Abstract: The present invention provides modified glucagon-like peptide 1 (GLP1) polypeptides, fusion proteins comprising modified GLP1 polypeptides, and methods of use thereof. In various embodiments of the invention, the fusion proteins are GLP1 receptor agonists that comprise a modified GLP1 fused to a stabilizing domain. In some embodiments, the fusion proteins comprising modified GLP1 are useful for treating or ameliorating a symptom or indication of a disorder such as obesity and diabetes.

Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Abstract: A visual indicator of lock status is disclosed. An operation indicator signaling to an operator a lock operator input direction and an unlock operator input direction to signal to the operator operations that will lock and unlock the locking device is also disclosed.

Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode structure and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.

Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first interconnect dielectric layer over a substrate and surrounding a first interconnect. A second interconnect dielectric layer is over the first interconnect dielectric layer and surrounds at least a part of a second interconnect. A bottom electrode is over the substrate, a top electrode is over the bottom electrode, and a ferroelectric layer is between the bottom electrode and the top electrode. The ferroelectric layer includes a lower horizontally extending portion, an upper horizontally extending portion arranged above the lower horizontally extending portion, and a vertically extending portion coupling the lower horizontally extending portion and the upper horizontally extending portion. The vertically extending portion extends through the first interconnect dielectric layer and the second interconnect dielectric layer.

Abstract: Modified glucagon-like peptide (GLP1) fusion proteins with modified GLP1 polypeptides and related methods of use are described. Aspects of the disclosure further relate to fusion proteins that are GLP1 receptor agonists with a modified GLP1 fused to a stabilizing domain such as an extra cellular domain or antibody. Fusion proteins with modified GLP1 that are useful for treating or ameliorating a symptom or indication of a blood sugar disorder such as obesity and diabetes are also provided.

Abstract: A carbon nanotube composite structure includes a carbon nanotube and a film-like structure. The carbon nanotube includes a p-type portion and an n-type portion. The film-like structure is a molybdenum disulfide film or a tungsten disulfide film, and the film-like structure covers the n-type portion.

Abstract: An optical system applied to an optical biometer is disclosed. The optical system includes a light source, first and second switchable reflectors, and first and second fixed reflectors. The first switchable reflector is disposed corresponding to the light source. The second switchable reflector is disposed corresponding to an eye. In a first mode, the first and second switchable reflectors are switched to a first state, and the incident light emitted by the light source is reflected by the first fixed reflector along a first optical path and then emitted to a first position of the eye. In a second mode, the first and second switchable reflectors are switched to a second state, and the incident light is sequentially reflected by the first switchable reflector, the second fixed reflector and the second switchable reflector along a second optical path and then emitted to a second position of the eye.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer and a first seed layer are arranged between the bottom electrode and the top electrode. A second seed layer continuously extends between a lower surface physically contacting the ferroelectric switching layer and an upper surface physically contacting the top electrode. The first seed layer, the second seed layer, and the ferroelectric switching layer include non-monoclinic crystal phases.

Abstract: The present invention provides modified glucagon-like peptide 1 (GLP1) polypeptides, fusion proteins comprising modified GLP1 polypeptides, and methods of use thereof. In various embodiments of the invention, the fusion proteins are GLP1 receptor agonists that comprise a modified GLP1 fused to a stabilizing domain. In some embodiments, the fusion proteins comprising modified GLP1 are useful for treating or ameliorating a symptom or indication of a disorder such as obesity and diabetes.

Abstract: A quantization method and apparatus for a text feature extraction model, and a device and a storage medium. The method includes: in a training process of a text feature extraction model, determining, according to a target quantization parameter, a quantization interval corresponding to the target quantization parameter, where the quantization interval includes a part of floating-point values of the target quantization parameter; constructing a mapping relationship between floating-point values and fixed-point values of the target quantization parameter based on the quantization interval, where a floating-point value smaller than a left end point of the quantization interval—is mapped to a quantized minimum fixed-point value, and a floating-point values larger than a right end point of the quantization interval is mapped to a quantized maximum fixed-point value; and performing a quantization operation on the target quantization parameter based on the mapping relationship.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.