Patents by Inventor Yang Wei

Yang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120030
    Abstract: The present application provides a method for analyzing droplets on the basis of volume distribution including obtaining a total volume V of a sample containing target molecules based on a system prepared using the sample. The system is emulsified into droplets. A droplet system is obtained when the droplets obtaining the sample executes an amplification reaction. A droplet image of the droplet system is obtained. A total number n of droplets included in the droplet system is obtained based on the droplet image. A droplet volume distribution of the droplet system is obtained based on the droplet image. A number j of negative droplets among the n droplets is counted. A quantitative analysis is performed for the target molecules according to the total volume V of the sample, the total number n of droplets, the droplet volume distribution information, and the number j of negative droplets.
    Type: Application
    Filed: January 13, 2021
    Publication date: April 11, 2024
    Inventors: YUN XIA, XIA ZHAO, YANG XI, YI WEI, FANG CHEN, HUI JIANG
  • Publication number: 20240115713
    Abstract: Disclosed are a polyethylene glycol conjugate drug, and a preparation method therefor and the use thereof. Specifically, the present invention relates to a polyethylene glycol conjugate drug represented by formula A or a pharmaceutically acceptable salt thereof, a method for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, an intermediate for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, and the use of the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof in the preparation of a drug.
    Type: Application
    Filed: July 21, 2021
    Publication date: April 11, 2024
    Inventors: Gaoquan LI, Nian LIU, Yongchen PENG, Xiafan ZENG, Gang MEI, Sheng GUAN, Yang GAO, Shuai YANG, Yifeng YIN, Jie LOU, Huiyu CHEN, Kun QIAN, Yusong WEI, Qian ZHANG, Dajun LI, Xiaoling DING, Xiangwei YANG, Liqun HUANG, Xi LIU, Liwei LIU, Zhenwei LI, Kaixiong HU, Hua LIU, Tao TU
  • Patent number: 11956079
    Abstract: Aspects of the disclosure relate to rate-matching a stream of bits encoded using polar codes. An exemplary method generally includes determining a mother code size (N) for transmitting an encoded stream of bits based, at least in part, on a minimum supported code rate for transmitting the encoded stream of bits (Rmin), a control information size of the encoded stream of bits (K), a number of coded bits for transmission (E), and a maximum mother code size (Nmax), encoding a stream of bits using a polar code of size (N, K) and storing the encoded stream of bits in a circular buffer, and performing rate-matching on the stored encoded stream of bits based, at least in part, on a comparison among the mother code size (N), the control information size of the encoded stream of bits (K), and the number of coded bits for transmission (E).
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: April 9, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Chao Wei, Jing Jiang, Jilei Hou, Yang Yang, Gabi Sarkis
  • Publication number: 20240114597
    Abstract: A graphene heating chip includes a substrate, an insulating layer, a graphene film, and a plurality of electrodes. The substrate has two opposite a first surface and a second surface, and the substrate defines a through hole. The insulating layer is suspended on the substrate. The insulating layer covering the through hole and not in direct contact with the first surface is defined as a window, and a plurality of grooves are formed on the window. The graphene film covers the window, and the graphene film includes a first graphene film portion and a second graphene film portion, and the first graphene film portion and the second graphene film portion are spaced apart from each other. The plurality of electrodes are located on the surface of the insulating layer away from the substrate. The present application also provides a method for making the graphene heating chip.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 4, 2024
    Inventors: LIANG LIANG, JIE ZHAO, YANG WEI, QUN-QING LI, SHOU-SHAN FAN
  • Publication number: 20240110838
    Abstract: A graphene heating chip includes a substrate, an insulating layer, a graphene film, and a plurality of electrodes. The substrate has two opposite a first surface and a second surface, and the substrate defines a through hole. The insulating layer is suspended on the substrate. The insulating layer covering the through hole and not in direct contact with the first surface is defined as a window, and a plurality of grooves are formed on the window. The graphene film covers the window, and the graphene film includes a first graphene film portion and a second graphene film portion, and the first graphene film portion and the second graphene film portion are spaced apart from each other. The plurality of electrodes are located on the surface of the insulating layer away from the substrate. The present application also provides a method for calibrating a temperature of the graphene heating chip.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 4, 2024
    Inventors: JIE ZHAO, LIANG LIANG, YANG WEI, QUN-QING LI, SHOU-SHAN FAN
  • Patent number: 11940187
    Abstract: A water treatment system of coupling a heat pump with multi-effect evaporation that comprises a lithium bromide absorption-type heat pump circulation system, a multi-effect evaporation circulation system and a compression-type heat pump circulation system is provided. The vapor in a tail-end evaporator of the multi-effect evaporation circulation system is introduced into a generator in the absorption-type heat pump to release heat and condense. A dilute solution in an absorber of the absorption-type heat pump is introduced into a first-effect evaporator to be evaporated by a treated water, and a condensation heat of the vapor generated by the generator of the absorption-type heat pump is recovered by an evaporator of a compressor heat pump, and another air source evaporator absorbs heat from ambient air to supply heat for the generator by a heat pump condenser.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 26, 2024
    Assignee: JIANGSU UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jiubing Shen, Lele Jiang, Wenbin Wei, Yang Chen
  • Patent number: 11934060
    Abstract: Provided is an array substrate. The array substrate includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines disposed on the base substrate. The data lines have a plurality of first extending parts and a plurality of second extending parts which are in an alternating arrangement. When the array substrate is used to prepare a liquid crystal display panel and the liquid crystal display panel is displaying, in each column of the sub-pixels, the voltage polarities of the two adjacent sub-pixels which respectively belong to two adjacent first pixel regions are opposite.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: March 19, 2024
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bo Feng, Shijun Wang, Yang Wang, Zhan Wei, Wenkai Mu, Yi Liu, Li Tian
  • Publication number: 20240086090
    Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Yang Lu, Yu-Sheng Hsu, Kang-Yong Kim, Ke Wei Chan
  • Publication number: 20240088171
    Abstract: An array substrate and display device are provided. The array substrate includes a base substrate, and gate lines, data lines, compensation blocks and sub-pixels located on the base substrate. Two gate lines are arranged between two adjacent rows of sub-pixels. The data lines are provided with multiple first extensions and second extensions arranged alternately. The extending direction of the first extensions intersects with the extending direction of the second extensions.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Wenkai MU, Shijun WANG, Yi LIU, Bo FENG, Yang WANG, Zhan WEI, Li TIAN
  • Publication number: 20240082245
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: November 3, 2023
    Publication date: March 14, 2024
    Inventors: Christine Collins, Bo Fu, Abhishek Gulati, Jens Kort, Matthew Kosloski, Yang Lei, Chih-Wei Lin, Ran Liu, Federico Mensa, Iok Chan NG, Tami Pilot-Matias, David Pugatch, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhen Zhang
  • Patent number: 11928752
    Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: March 12, 2024
    Assignee: GRABTAXI HOLDINGS PTE. LTD.
    Inventors: Kong-Wei Lye, Yang Cao, Swara Desai, Chen Liang, Xiaojia Mu, Yuliang Shen, Sien Y. Tan, Muchen Tang, Renrong Weng, Chang Zhao
  • Publication number: 20240077519
    Abstract: A probe card, a method for designing the probe card, a method for producing a tested semiconductor device, a method for testing an unpackaged semiconductor by the probe card, a device under test, and a probe system are provided. The probe card includes a wiring substrate, a connection carrier board, and a probe device. At least two probes form a differential pair electrically connected to a loopback line of the connection carrier board to form a test signal loopback path. The probe device has a probe device impedance on the test signal loopback path. The loopback line has a loopback line impedance on the test signal loopback path. A difference between the probe device impedance on the test signal loopback path and the loopback line impedance on the test signal loopback path is in an impedance range.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Yang-Hung Cheng, Yu-Hao Chen, Jhin-Ying Lyu, Hao Wei
  • Patent number: 11916127
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Publication number: 20240063296
    Abstract: The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.
    Type: Application
    Filed: July 12, 2023
    Publication date: February 22, 2024
    Inventors: GUANG-QI ZHANG, YANG WEI, SHOU-SHAN FAN
  • Publication number: 20240064998
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
  • Publication number: 20240063299
    Abstract: The present application provides an inverter. The inverter includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form air gaps, and the air gaps are distributed at both sides of the bottom electrode. The gate electrode is configured to connect with a signal input terminal, the bottom electrode is configured to connect with a signal output terminal.
    Type: Application
    Filed: July 12, 2023
    Publication date: February 22, 2024
    Inventors: GUANG-QI ZHANG, YANG WEI, SHOU-SHAN FAN
  • Publication number: 20240047565
    Abstract: A field effect transistor includes a gate electrode, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer is located on the surface of the gate electrode, and the channel layer is located on the surface of the insulating layer away from the gate electrode. The source electrode and the drain electrode are spaced apart from each on the surface of the channel layer away from the insulating layer. The source electrode and the drain electrode are one-dimensional structures. The present application further provides a method for making the field effect transistor.
    Type: Application
    Filed: March 30, 2023
    Publication date: February 8, 2024
    Applicants: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: XUAN-ZHANG LI, YANG WEI, SHOU-SHAN FAN, YUE-GANG ZHANG
  • Publication number: 20240033077
    Abstract: A prosthetic heart valve is constructed from a flexible substrate that can be folded from an unfolded configuration to a folded configuration, in which the prosthesis is operable as a prosthetic heart valve. The prosthetic heart valves can be designed as atrioventricular valves (e.g., tricuspid valve, mitral valve) or as semilunar valves (e.g., aortic valve, pulmonary valve).
    Type: Application
    Filed: October 1, 2021
    Publication date: February 1, 2024
    Inventors: Brandon James Tefft, Yang Wei William Yuan
  • Publication number: 20240036100
    Abstract: A field effect transistor includes a gate electrode, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer is located on the surface of the gate electrode, and the channel layer is located on the surface of the insulating layer away from the gate electrode. The source electrode and the drain electrode are spaced apart from each on the surface of the channel layer away from the insulating layer. The source electrode and the drain electrode are one-dimensional structures. The present application further provides a method for making the field effect transistor and a method for measuring an interface resistance of the field effect transistor.
    Type: Application
    Filed: March 30, 2023
    Publication date: February 1, 2024
    Inventors: XUAN-ZHANG LI, YANG WEI, SHOU-SHAN FAN, YUE-GANG ZHANG
  • Publication number: 20240023807
    Abstract: An optical biometer including a light source, a first-stage coupler, a first and a second second-stage coupler, a first and a second optical path difference generator, a first and a second optical component set, a first and a second detection device is disclosed. The first-stage coupler receives an incident light from the light source and emits first and second first-stage lights. The first second-stage coupler receives the first first-stage light and emits first and second second-stage lights. The second second-stage coupler receives the second first-stage light and emits third and fourth second-stage lights. The first/second optical path difference generator generates the first/fourth second-stage light with the first/second optical path difference. The first/second optical component set emits the second/third second-stage light to a first/second position of an eye and receives a first/second reflected light. The first/second detector receives a first/second detection light.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 25, 2024
    Inventors: Che-Liang TSAI, William WANG, Chung-Ping CHUANG, Sung-Yang WEI, Hsuan-Hao CHAO, Chung-Cheng CHOU