Patents by Inventor Yanxiang Liu
Yanxiang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8835292Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.Type: GrantFiled: October 31, 2012Date of Patent: September 16, 2014Assignees: International Business Machines Corporation, Global Foundries, Inc.Inventors: Michael P. Chudzik, Min Dai, Xiang Hu, Jinping Liu, Yanxiang Liu, Xiaodong Yang
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Patent number: 8809178Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.Type: GrantFiled: February 29, 2012Date of Patent: August 19, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
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Patent number: 8809962Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.Type: GrantFiled: August 26, 2011Date of Patent: August 19, 2014Assignees: GlobalFoundries Inc., GlobalFoundries Singapore Pte. Ltd., International Business Machines CorporationInventors: Yanxiang Liu, Jinping Liu, Min Dai, Xiaodong Yang
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Publication number: 20140227845Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.Type: ApplicationFiled: February 14, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Yanxiang Liu, Manfred Eller, Johannes van Meer
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Publication number: 20140120708Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Min Dai, Xiang Hu, Jinping Liu, Yanxiang Liu, Xiaodong Yang
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Publication number: 20140103420Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Yanxiang Liu, Vara Vakada, Jerome Ciavatti
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Patent number: 8691646Abstract: A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N? doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.Type: GrantFiled: May 3, 2012Date of Patent: April 8, 2014Assignee: GlobalFoundries Inc.Inventors: Yanxiang Liu, Jerome Ciavatti
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Patent number: 8669616Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.Type: GrantFiled: September 13, 2013Date of Patent: March 11, 2014Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Xiaodong Yang, Yanxiang Liu, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai
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Patent number: 8664717Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.Type: GrantFiled: January 9, 2012Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Young Way Teh, Vara Vakada
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Patent number: 8637372Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.Type: GrantFiled: June 29, 2011Date of Patent: January 28, 2014Assignee: Globalfoundries, Inc.Inventors: Yanxiang Liu, Xiaodong Yang, Jinping Liu
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Publication number: 20140015020Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.Type: ApplicationFiled: September 13, 2013Publication date: January 16, 2014Inventors: Xiaodong YANG, Yanxiang LIU, Vara Govindeswara Reddy VAKADA, Jinping LIU, Min DAI
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Publication number: 20130292745Abstract: A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N? doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Jerome Ciavatti
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Patent number: 8557668Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.Type: GrantFiled: January 12, 2012Date of Patent: October 15, 2013Assignee: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.Inventors: Xiaodong Yang, Yanxiang Liu, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai
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Publication number: 20130224945Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.Type: ApplicationFiled: February 29, 2012Publication date: August 29, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans Van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
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Publication number: 20130181260Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd., GLOBALFOUNDRIES Inc.Inventors: Xiaodong Yang, Yanxiang Liu, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai
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Publication number: 20130175617Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.Type: ApplicationFiled: January 9, 2012Publication date: July 11, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Yanxiang Liu, Young Way Teh, Vara Vakada
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Publication number: 20130049142Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicants: International Business Machines Corporation, GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Yanxiang Liu, Jinping Liu, Min Dai, Xiaodong Yang
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Publication number: 20130032890Abstract: CMOS devices (60, 61, 61?) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62?, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61?) are less likely to go into latch-up with increasing operating temperature.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Inventors: Yanxiang Liu, Xiaodong Yang, Gan Wang
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Publication number: 20130005103Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Yanxiang Liu, Xiaodong Yang, Jinping Liu
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Publication number: 20110284985Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.Type: ApplicationFiled: May 20, 2010Publication date: November 24, 2011Applicant: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Bin Yang