Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

Abstract: An integrated circuit for detecting and correcting error events associated with atomic particles includes error detection circuitry connected to monitoring circuitry. The error detection circuitry may include a particle sensing circuit (e.g., a diode circuit) embedded below a substrate surface of the integrated circuit, and a particle validation circuit (e.g., a sense amplifier) coupled to the particle sensing circuit through a conductive via. The particle sensing circuit may detect and collect stray charges generated by an atomic particle passing through the integrated circuit. A particle validation circuit may generate an output signal that is indicative of the particle energy of the atomic particle based on the collected stray charge by the particle sensing circuit. Monitoring circuitry may identify the particle energy based on the output signal and subsequently generate an error correction signal, which activates error correction operations in the integrated circuit.

Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.

Abstract: A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2n level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.

Abstract: Illustratively, a finFET comprises at least one fin, and typically several fins, with a trapping region in or on a substrate at the base of each fin to trap ions produced by radiation incident on the substrate. In one embodiment, the trapping region is an implanted region having a conductivity type opposite that of the substrate. In another, the trapping region is a defect region. In another, the trapping region is an epitaxial region grown on the substrate. The finFET is formed by forming the fin or fins and then forming the trapping region at the base of the fin. Illustratively, the trapping region is formed by implanting in the substrate ions having a conductivity type opposite that of the substrate or by creating defects in the substrate or by epitaxially growing a region or regions having an opposite conductivity type to that of the substrate.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: Circuitry may include a substrate with an input and an output circuit coupled in series at an intermediate node. The output circuit may have an output transistor and a stack transistor coupled in series between an output node and a voltage supply terminal. The two circuits may be placed on the substrate such that a single event transient charge injected into a sensitive diffusion of the intermediate node is shared through the substrate with the sensitive diffusion of the stack transistor of the output circuit. The charge sharing may reduce the recovery time at the output node and help to reduce the recovery time at the intermediate node, thereby providing increased single event transient robustness and reducing the probability of a permanent flip of the intermediate node and the output node of the circuitry.

Abstract: An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.

Abstract: An illustrative finFET comprises first, second, and third pluralities of fins having gate structures and source and drain regions formed on the fins so that first PMOS transistors are formed in first epitaxial regions on the first plurality of fins, NMOS transistors are formed in second epitaxial regions on the second plurality of fins and second PMOS transistors are formed in third epitaxial regions on the third plurality of fins. In three embodiments, the fins are formed in silicon; the first epitaxial region is silicon germanium; the second region is silicon; and the third region is 1) silicon, 2) silicon carbide, or 3) silicon or silicon carbide on a silicon carbide cladding. In another embodiment, the third epitaxial regions are wide band gap semiconductors formed on wide band gap semiconductor fins. In another embodiment, all the fins and epitaxial regions are wide band gap semiconductors.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a transition accelerator circuit are disclosed. A disclosed circuit includes an inverter with an input, first and second power supply inputs, and an output. The input may receive an input signal from an external component. A first multiplexer, operable to couple either a first voltage level or a second voltage level to the first power supply input based on a control input, is coupled to the first power supply input of the inverter. An input of a delay circuit is coupled to the output of the inverter and an output of the delay circuit is coupled to the control input of the first multiplexer.

Abstract: Integrated circuits with bipolar transistors are provided. In one embodiment, a bipolar transistor may include an emitter region, a first base region that surrounds the emitter region, a collector region that surrounds the first base region, and a second base region that surrounds the collector region. Respective well taps may be formed within the emitter, collector, and the second base regions. A deep doped well having the same doping type as the base regions may extend beneath the emitter, collector, and base regions. In another embodiment, the bipolar transistor may include an emitter region, a base region that surrounds the emitter region, and a collector region that surrounds the base region. Respective well taps may be formed within the emitter, base, and collector regions. A deep doped well having the same doping type as the base region may extend beneath the emitter and only a portion of the base region.

Abstract: A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower portion of the semiconductive material has doping of a first conductivity type and forms a collector and an upper portion of the semiconductive material has doping of a second conductivity type and forms a base. Either a metal or a polysilicon emitter is formed on the base. An illustrative method for forming the BJT comprises forming first and second layers of a semiconductive material having first and second conductivity types, respectively; forming a hard mask on an upper surface of the second layer; using the hard mask to etch first and second channels in the semiconductive material on first and second opposing sides of the hard mask; removing the hard mask; and forming an emitter on the upper surface of the second layer.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.

Abstract: A flue gas-treating method for treating acid tail gas by using an ammonia process, comprising the following steps of: 1) controlling the concentration of sulfur dioxide in an acid tail gas entering an absorber to be ?30,000 mg/Nm3; 2) spraying and cooling with a process water or/and an ammonium sulfate solution in the inlet duct of the absorber or inside the absorber; 3) providing an oxidation section in the absorber, wherein the oxidation section is provided with oxidation distributors for oxidizing the desulfurization absorption solution; 4) providing an absorption section in the absorber wherein the absorption section achieves desulfurization spray absorption by using absorption solution distributors via an absorption solution containing ammonia; the absorption solution containing ammonia is supplied by an ammonia storage tank; 5) providing a water washing layer above the absorption section in the absorber, wherein the water washing layer washes the absorption solution in the tail gas to reduce the slip of

Abstract: Integrated circuits with clocked storage elements are provided. A clocked storage element such as a flip-flop circuit may include a master latch, a slave latch, and associated control circuitry. The master and slave latches may be implemented using dual-interlocked cell (DICE) latch configurations. The DICE latch may include at least four inverting circuits having two redundant node pairs and may exhibit immunity to soft error upset (SEU) events. Each of the master and slave latches may be separated into different portions so that the redundant nodes are physically separated by interposing circuitry. The redundant nodes may also be formed in separate wells to further minimize charge sharing. The different portions of the master and slave latch may be interleaved to minimize area.

Abstract: An IC design that has an ESD transistor is disclosed. The IC includes a transistor, a ballast resistor, a routing structure and a coupling. The transistor includes a gate, a source and a drain. The ballast resistor is extending parallel to the gate of the transistor. The coupling connects the source of the drain of the transistor the ballast resistor. The routing structure connects the ballast resistor to the remaining of the circuitry. A method to design the IC is also disclosed. The ESD transistor provides means of protection against the ESD surges.

Abstract: A flue gas-treating method for treating acid tail gas by using an ammonia process, comprising the following steps of: 1) controlling the concentration of sulfur dioxide in an acid tail gas entering an absorber to be ?30,000 mg/Nm3; 2) spraying and cooling with a process water or/and an ammonium sulfate solution in the inlet duct of the absorber or inside the absorber; 3) providing an oxidation section in the absorber, wherein the oxidation section is provided with oxidation distributors for oxidizing the desulfurization absorption solution; 4) providing an absorption section in the absorber wherein the absorption section achieves desulfurization spray absorption by using absorption solution distributors via an absorption solution containing ammonia; the absorption solution containing ammonia is supplied by an ammonia storage tank; 5) providing a water washing layer above the absorption section in the absorber, wherein the water washing layer washes the absorption solution in the tail gas to reduce the slip of

Abstract: A flue gas-treating method for treating acid tail gas by using an ammonia process, comprising the following steps of: 1) controlling the concentration of sulfur dioxide in an acid tail gas entering an absorber to be ?30,000 mg/Nm3; 2) spraying and cooling with a process water or/and an ammonium sulfate solution in the inlet duct of the absorber or inside the absorber; 3) providing an oxidation section in the absorber, wherein the oxidation section is provided with oxidation distributors for oxidizing the desulfurization absorption solution; 4) providing an absorption section in the absorber wherein the absorption section achieves desulfurization spray absorption by using absorption solution distributors via an absorption solution containing ammonia; the absorption solution containing ammonia is supplied by an ammonia storage tank; 5) providing a water washing layer above the absorption section in the absorber, wherein the water washing layer washes the absorption solution in the tail gas to reduce the slip of