Patents by Inventor Yanzhong Xu
Yanzhong Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150318029Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: ApplicationFiled: May 2, 2014Publication date: November 5, 2015Inventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Patent number: 8995175Abstract: A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.Type: GrantFiled: January 13, 2012Date of Patent: March 31, 2015Assignee: Altera CorporationInventors: Jun Liu, Irfan Rahim, Yanzhong Xu, Andy L. Lee
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Patent number: 8975928Abstract: Input-output (IO) buffer circuitry is provided that is operable to drive signals off an integrated circuit. The input-output circuitry may include an input-output driver having an asymmetric transistor and/or a low-threshold voltage transistor. The asymmetric transistor may include a first source-drain region at a first dopant concentration level and a second source-drain region at a second dopant concentration level. The first dopant concentration level and the second dopant concentration level may be different. The IO buffer circuitry may be able to prevent issues with regards to hot carrier injection when driving signals with elevated voltages. The IO buffer circuit may also be manufactured without increasing the overall cost.Type: GrantFiled: April 26, 2013Date of Patent: March 10, 2015Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu
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Patent number: 8873278Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.Type: GrantFiled: January 2, 2013Date of Patent: October 28, 2014Assignee: Altera CorporationInventors: Yanzhong Xu, Jeffrey T. Watt
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Publication number: 20140245113Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.Type: ApplicationFiled: May 5, 2014Publication date: August 28, 2014Applicant: Altera CorporationInventor: Yanzhong Xu
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Patent number: 8750026Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: June 20, 2013Date of Patent: June 10, 2014Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Patent number: 8739010Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.Type: GrantFiled: November 19, 2010Date of Patent: May 27, 2014Assignee: Altera CorporationInventor: Yanzhong Xu
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Patent number: 8705300Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with each row of memory cells and data lines may be associated with each column of memory cells. Precharge driver circuitry may be used to precharge the data lines to a precharge voltage prior to performing read operations. The integrated circuit may contain core logic that is powered using a core logic power supply voltage. The precharge voltage may be reduced with respect to the core logic power supply voltage. Each address transistor may have a body bias terminal. The integrated circuit may contain programmable voltage regulator circuitry that produces a body bias for the address transistors based on a body bias setting stored in nonvolatile memory on the integrated circuit.Type: GrantFiled: August 4, 2010Date of Patent: April 22, 2014Assignee: Altera CorporationInventors: Yanzhong Xu, Jeffrey T. Watt
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Publication number: 20140085967Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.Type: ApplicationFiled: November 27, 2013Publication date: March 27, 2014Applicant: Altera CorporationInventors: Lin-Shih Liu, Mark T. Chan, Yanzhong Xu, Irfan Rahim, Jeffrey T. Watt
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Patent number: 8643108Abstract: One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.Type: GrantFiled: August 19, 2011Date of Patent: February 4, 2014Assignee: Altera CorporationInventors: Irfan Rahim, Jeffrey T. Watt, Yanzhong Xu, Lin-Shih Liu
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Patent number: 8630113Abstract: An integrated circuit (IC) includes a memory circuit. The memory circuit includes a plurality of thyristors. The plurality of thyristors are coupled in tandem.Type: GrantFiled: November 25, 2008Date of Patent: January 14, 2014Assignee: Altera CorporationInventors: Yanzhong Xu, Jeffrey T. Watt
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Patent number: 8611137Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.Type: GrantFiled: November 23, 2011Date of Patent: December 17, 2013Assignee: Altera CorporationInventors: Lin-Shih Liu, Mark T. Chan, Yanzhong Xu, Irfan Rahim, Jeffrey T. Watt
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Patent number: 8519403Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.Type: GrantFiled: February 4, 2011Date of Patent: August 27, 2013Assignee: Altera CorporationInventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
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Patent number: 8482963Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: December 2, 2009Date of Patent: July 9, 2013Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Publication number: 20130127494Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Inventors: Lin-Shih Liu, Mark T. Chan, Yanzhong Xu, Irfan Rahim, Jeffrey T. Watt
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Publication number: 20130043536Abstract: One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.Type: ApplicationFiled: August 19, 2011Publication date: February 21, 2013Inventors: Irfan RAHIM, Jeffrey T. WATT, Yanzhong XU, Lin-Shih LIU
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Patent number: 8355292Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.Type: GrantFiled: September 30, 2009Date of Patent: January 15, 2013Assignee: Altera CorporationInventors: Yanzhong Xu, Jeffrey T. Watt
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Publication number: 20120131424Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.Type: ApplicationFiled: November 19, 2010Publication date: May 24, 2012Inventor: Yanzhong Xu
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Patent number: 8077500Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.Type: GrantFiled: June 22, 2010Date of Patent: December 13, 2011Assignee: Altera CorporationInventors: Yanzhong Xu, Jeffrey T. Watt
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Patent number: 7883946Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.Type: GrantFiled: May 8, 2008Date of Patent: February 8, 2011Assignee: Altera CorporationInventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu