Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Abstract: Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

Abstract: The present invention is directed to a test structure and method to determine the effects of the well proximity effect on the gate threshold voltage of FETs at different distances from the edge of the well.

Abstract: A latch circuit comprises eight MOS transistors in which a first pair of transistors are connected in series between a voltage supply node and ground and a second pair of transistors are connected in parallel to the first pair between the voltage supply node and ground. A fifth transistor is connected between the gates of the first pair and a node between the transistors of the second pair and a sixth transistor is connected between the gates of the second pair and a node between the transistors of the first pair. The seventh transistor is a write transistor connected between a data in line and the node between the first pair of transistors and the eighth transistor is a clear transistor connected between the node between the second pair of transistors and ground.

Abstract: Integrated circuit varactors and methods for varactor fabrication are provided. Varactors are formed on integrated circuits that contain complementary metal-oxide-semiconductor (CMOS) transistors. The same semiconductor fabrication process steps are used to form both the varactors and CMOS transistors, thereby eliminating potentially cost-prohibitive changes to manufacturing process flows. Varactor performance is enhanced by including a deep n-well structure. The deep n-well reduces sheet resistance in the semiconductor portion of the varactor and improves the varactor's quality factor. The deep n-well is formed from the same deep n-well layer that is used to form the CMOS transistors on the integrated circuit. The varactor has two active electrodes. The electrodes are spaced farther apart than specified by semiconductor fabrication design rules. The number of contact vias used in one of the electrodes is less than the maximum specified by the design rules.

Abstract: In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.

Abstract: In one embodiment, the threshold voltage of a first transistor is adjusted by implanting a dopant through a mask (e.g., photoresist material). The thickness of the mask may be varied to obtain a particular threshold voltage. The mask may be formed such that it covers a first transistor region where the first transistor is to be fabricated, while leaving a second transistor region exposed. This allows an implant step to adjust the threshold voltage of the first transistor and to form a well in the second transistor region.

Abstract: The invention discloses a comb wavelength division multiplexer, comprising: an input device at input side, a polarization splitter, a &lgr;/2 phase delay wave plate; a birefringent crystal filter; and a reflective parallel light polarization splitter for reflecting an incident light beam from the birefringent crystal filter into the birefringent crystal filter again, and passing the reflected light beam through the &lgr;/2 phase delay wave plate and the polarization splitter to an output side, so that the input side and the output side are a same side. The invention uses only one-stage filter to obtain a two-stage filtering effect. The channel isolation factor is improved and the size of the apparatus is reduced (FIG. 2).