Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a base substrate, a display region including a first region, a second region and a transition region; first light-emitting elements at the first region; second light-emitting elements, first pixel circuitries and second pixel circuitries at the transition region, each first pixel circuitry being arranged between adjacent second pixel circuitries, an orthogonal projection of at least one second pixel circuitry onto the base substrate at least partially overlapping an orthogonal projection of at least one second light-emitting element onto the base substrate; first conductive lines each coupled between at least one first pixel circuitry and at least one first light-emitting element; and second conductive lines each coupled to at least one first pixel circuitry and extending along the at least one first pixel circuitry to a side away from the at least one first light-emitting element.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.

Abstract: Disclosed in the embodiments of the present disclosure are a display panel and a display device. The display panel includes: a display area and a peripheral area surrounding the display area, the display area includes a first display area and a second display area; a plurality of virtual pixel circuits and a plurality of drive pixel circuits, the plurality of virtual pixel circuits are arranged in the peripheral area, and the plurality of drive pixel circuits are arranged in the second display area; the plurality of first light emitting devices are arranged in the first display area, and the plurality of second light emitting devices are arranged in the second display area; the virtual pixel circuit is electrically connected with the first light emitting device, and the drive pixel circuit is electrically connected with the second light emitting device.

Abstract: A communication apparatus includes: control circuitry that controls transmission/reception of a first control frame and a first data frame used for communication with another communication apparatus, and controls transmission/reception of a second control frame and a second data frame used for communication with the another communication apparatus; first radio circuitry that performs radio communication of the first control frame and the first data frame using a first omni-directional antenna; and second radio circuitry that performs radio communication of the second control frame and the second data frame using a second directional antenna.

Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bit line structure positioned on the substrate; a plurality of first bit line spacers positioned on sidewalls of the bit line structure; a plurality of second bit line spacers positioned on the plurality of first bit line spacers. The plurality of first bit line spacers include one or more species of vanadium oxide. The plurality of second bit line spacers include silicon nitride, silicon nitride oxide, or silicon oxynitride.

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bit line structure positioned on the substrate; a plurality of first bit line spacers positioned on sidewalls of the bit line structure; a plurality of second bit line spacers positioned on the plurality of first bit line spacers. The plurality of first bit line spacers include one or more species of vanadium oxide. The plurality of second bit line spacers include silicon nitride, silicon nitride oxide, or silicon oxynitride.

Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

Abstract: A memory includes at least a target word line and a first word line group and a second word line group respectively stacked on both sides of the target word line. The first word line group includes first word lines, and the second word line group includes second word lines. A method for operating the memory includes, during a pre-charge operation, applying a first bias voltage signal to the plurality of first word lines, applying a second bias voltage signal to a target word line, and applying a third bias voltage signal to the plurality of second word lines. The method also includes, during a programming operation, applying a program voltage signal to a target word line.

Abstract: The present application discloses a semiconductor device with a decoupling unit. The semiconductor device includes a first tier structure including conductive features of positioned over a substrate, and a decoupling unit the first tier structure positioned between the conductive features; a first-tier-alignment mark positioned on the decoupling unit, and including a fluorescence material; a second tier structure positioned on the first tier structure and including conductive features positioned over and deviated from the conductive features of the first tier structure, and a decoupling unit of positioned over the first tier structure, and positioned between the conductive features of the second tier structure; and a second-tier-alignment mark positioned on the decoupling unit of the second tier structure, and including a fluorescence material. The decoupling units include a low-k dielectric material and respectively include a bottle-shaped cross-sectional profile.

Abstract: A transformer device includes a first and a second trace, a first and a second connection member, and a first input/output member. A second sub-trace of the first trace is coupled to a first sub-trace of the first trace at a first and a second area. The first connection member is coupled to the first and the second sub-trace. The first and a third sub-trace of the second trace are disposed in turn. A fourth sub-trace of the second trace is coupled to the third sub-trace at the first and the second area. The second and the fourth sub-trace are disposed in turn. The second connection member is coupled to the third and the fourth sub-trace. The first sub-trace includes first wires, and the first input/output member is coupled to the first wire which is located at an inner side among the first wires.

Abstract: A shift register unit including an input circuit configured to receive a first clock signal and an input signal to provide the input signal to a first node; a first control circuit electrically connected to the first node and a second node and configured to receive the first clock signal to control a voltage of the second node; an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal to provide an output signal to the output terminal based on the second clock signal; an output voltage control circuit electrically connected to the second node and the output terminal and configured to control a voltage of the output signal; and a discharge circuit electrically connected to the first node and the second node and configured to receive the second clock signal to achieve electrical discharge of the first node.

Abstract: A pixel driving circuit, including: a driving transistor, and first and second energy storage elements; a first reset sub-circuit configured to write an initialization voltage signal to a third node in response to a first reset signal; a second reset sub-circuit configured to, in response to a second reset signal, turn it conductive between a gate of the driving transistor and a fourth node and reset the two; a data writing sub-circuit configured to write a data voltage signal to the second energy storage element in response to a scanning signal; and a light emitting control sub-circuit configured to turn it conductive between a first electrode of the driving transistor and a power supply terminal in response to a first light emitting control signal, and transmit the data voltage signal to the gate of the driving transistor in response to a second light emitting control signal.

Abstract: A hydrocarbon resin polymer including a repeating unit (A) is derived from dicyclopentadiene (DCPD). The hydrocarbon resin polymer has a fluorine substituent, and the content of the fluorine substituent is 100 to 4500 ppm based on the total weight of the hydrocarbon resin polymer. A manufacturing method of the above hydrocarbon resin polymer. The manufacturing method includes polymerizing a mixture in the presence of a fluorine-containing compound, wherein the fluorine-containing compound is a boron trifluoride complex and the mixture includes a dicyclopentadiene. A substrate structure includes a resin layer, and a conductive layer disposed on the resin layer. The resin layer is formed from a resin composition including the above hydrocarbon resin polymer using a cross-linking process.

Abstract: In a pixel circuit, a data writing-in circuit is configured to control to connect the data line and the second end of the driving circuit under the control of a first scan signal provided by the first scan line; a reset circuit is configured to control to connect the reset voltage line and the second end of the driving circuit under the control of a third scan signal provided by the third scan line; or control to connect the reset voltage line and the first end of the driving circuit under the control of the third scan signal; a driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of a control end of the driving circuit.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. The interconnection structure has a first lateral surface and a second lateral surface. The first isolation feature is disposed on the first lateral surface of the interconnection structure. The second isolation feature is disposed on the second lateral surface of the interconnection structure. The first isolation feature is different from the second isolation feature.

Abstract: The present application discloses a display panel, a display device and a method for manufacturing a display panel. The display panel includes a first display area, including a plurality of first light emitting units and a first driving layer for driving the plurality of first light emitting units, and a second display area, at least partially surrounded by the first display area, and making ambient light at least partially transmitted. The first driving layer includes a first light shielding pattern, the first light shielding pattern at least partially surrounding the second display area and including a hollow structure which exposes at least part of the second display area.

Abstract: The present application relates to a shift register, a scanning driving circuit and a displaying device. The shift register includes a first inputting circuit, a first outputting circuit, a second inputting circuit, a second outputting circuit and a second controlling circuit. The second controlling circuit is electrically connected to a first node, a second node, a fifth voltage terminal, a second clock-signal terminal and a controlling terminal. The second controlling circuit is configured for, under the control of the signal of the second node, the control of a second clock signal and the control of the signal of the controlling terminal, when the first outputting circuit is switched on, disconnecting the electric connection between the first node and the fifth voltage terminal, and when the second outputting circuit is switched on, writing the signal of the fifth voltage terminal into the first node.

Abstract: Disclosed in embodiments of the present disclosure are a display substrate, a display panel and a display device. The display substrate includes a plurality of first light-emitting devices in a first display area, a plurality of second light-emitting devices in a second display area, a plurality of first pixel driving circuits in the second display area, the first pixel driving circuits are connected with the first light-emitting devices, and the plurality of pixel driving circuit has a drive transistor; gate connecting electrodes connected to a gate electrode of the drive transistor; a plurality of traces, each of at least part of the traces being electrically connected from the first pixel driving circuits across the gate connecting electrodes to the first light-emitting devices; and a shielding layer including isolation parts, an orthographic projection of the isolation parts at least partially overlapping an orthographic projection of the gate connecting electrodes.