Abstract: A superconducting quantum processor unit (QPU) comprising a resonator having a resonator frequency ?C coupled between a control qubit having a control frequency ?L and a target qubit having a target frequency ?R. The control frequency ?L is detuned from the target frequency ?R at less than a detuning gap of the resonator frequency ?C. A microwave drive applies to the resonator a resonator drive frequency ?cd at a drive strength substantially equal to a ZZ-free operating point 0 of a controlled phase for the control qubit, resonator, and target qubit to induce entanglement between the control and target qubits. The effective ZZ coupling between the control and target qubits vanishes at operating point 0. The resonator may be of either a 2D or a 3D high-coherence resonator type. Control and target qubits may be of a fixed-frequency transmon type (e.g., cross-resonance (CR) Controlled-NOT (CNOT) or adiabatic Controlled-Z (CZ)).

Abstract: The display substrate includes a drive circuit layer disposed on a base substrate and a light emitting structure layer, the drive circuit layer includes multiple circuit units, multiple first initial signal lines extending along a first direction, and multiple second initial signal lines and low-voltage power supply lines extending along a second direction, the circuit unit includes at least a pixel drive circuit, the light emitting structure layer includes multiple light emitting devices, the first initial signal line is configured to provide an initial voltage signal to the pixel drive circuit, the low-voltage power supply line is configured to provide a low power supply voltage signal to the light emitting device, the second initial signal line is connected to the first initial signal line, and the first initial signal lines and the second initial signal lines constitute a net-like connecting structure.

Abstract: An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.

Abstract: A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

Abstract: A display substrate includes at least two barrier layers in a peripheral area of the display substrate. The at least two barrier layers includes a first barrier layer forming an enclosure; and a third barrier layer on a side of the first barrier layer closer to a display area. The third barrier layer includes one or more discontinuous portions.

Abstract: A display panel, a manufacturing method thereof and a display device. The display panel includes a first region and a second region. The second region includes a driving circuitry layer and a first light-emitting unit located on a base substrate, the first region includes a plurality of second light-emitting units located on the base substrate, the second light-emitting unit is electrically coupled to the driving circuitry layer through a transparent conductive layer, the transparent conductive layer includes at least two conductive sub-layers laminated one on another and insulated from each other, each conductive sub-layer includes at least one transparent conductive line, and each transparent conductive line is coupled to a corresponding second light-emitting unit.

Abstract: The present disclosure provides industrially scalable methods of making (Z)-endoxifen or a salt thereof, crystalline forms of endoxifen, and compositions comprising them. The present disclosure also provides methods for treating hormone-dependent breast and hormone-dependent reproductive tract disorders.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels including a light emitting element and a pixel circuit, the light emitting element includes a second electrode including a main body electrode. The sub-pixels include a first color sub-pixel which includes a first connecting portion. In the first color sub-pixel, the connecting electrode is connected with the first connecting portion through a first via hole, and the first connecting portion is electrically connected with the pixel circuit through a first connecting hole; and the first via hole and the first connecting hole are not overlapped with the main body electrode, and orthographic projections of the first via hole and the first connection hole on a first straight line extending in an extension direction of the data line are overlapped.

Abstract: A display substrate and a display device. The display substrate includes a display region, a first connecting wire and a second connecting wire. The display region includes a first display region and a second display region. The first display region includes a plurality of light emitting devices arranged in an array, and the plurality of light emitting devices includes a first light emitting device and a second light emitting device. The second display region includes a plurality of first pixel circuit units, and the plurality of pixel circuit units includes a first pixel circuit and a second pixel circuit. The first connecting wire is connected to the first pixel circuit and the first light emitting device. The second connecting wire is connected to the second pixel circuit and the second light emitting device. The first direction and the second direction intersect each other.

Abstract: A semi-solid alloy thermal interface composition and method for dissipating heat from an electronic component using the same are disclosed in the present disclosure. The semi-solid alloy thermal interface material comprises, based on total atoms of 100 at. %, 0.1-10 at. % of Bi, 20-30 at. % of In, and 65-75 at. % of Sn. In a method for dissipating heat from an electronic component using the semi-solid alloy thermal interface material, the semi-solid alloy thermal interface material is disposed between a chip and a heat sink, wherein the semi-solid alloy thermal interface material is completely solid at a room-temperature, and has a liquid content ranging from 0.1 to 70 mol % based on a total mole of 100 mol % of the semi-solid alloy thermal interface composition at a temperature of 40 to 130° C.

Abstract: A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second first bottom electrode layer. The semiconductor device further includes a top electrode disposed over and surrounded by the bottom electrode structure. The top electrode has a ring shape from a top view. In addition, the semiconductor device includes an insulating layer separating the top electrode from the bottom electrode structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.

Abstract: A self-powered apparatus is used for various kinds of cycling and indoor exercise devices. The self-powered apparatus includes a pedal unit, a spindle, a generator and an energy storage element. The pedal unit includes an inner surface to form an accommodating space therein. The spindle is accommodated in the accommodating space. The generator includes a stator and a rotor. The stator is disposed on the spindle, the rotor is disposed on the inner surface of the pedal unit, and the rotor surrounds the stator correspondingly and is non-contact with the stator. The energy storage element is electrically coupled to the generator. When the pedal unit is being pedaled to rotate by a rider, the stator is fixed on the spindle, the rotor rotates relatively to the stator and along with the pedal unit, and a power is generated by the generator to charge the energy storage element.

Abstract: The present disclosure provides industrially scalable methods of making (Z)-endoxifen or a salt thereof, crystalline forms of endoxifin, and compositions comprising them. The present disclosure also provides methods for treating hormone-dependent breast and hormone-dependent reproductive tract disorders.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.

Abstract: A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first impurity region positioned in the substrate; a first dielectric layer positioned on the substrate; a first contact including a buried portion positioned along the first dielectric layer and on the first impurity region, and a protruding portion positioned on the buried portion and protruding from the first dielectric layer; a first top assistant cap covering the protruding portion; and a first top conductive layer positioned on the first top assistant cap. The first top assistant cap includes germanium or silicon germanium.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a first insulating layer positioned on a substrate; a bottom contact positioned in the first insulating layer; a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer sequentially stacked on the first insulating layer; and a conductive structure including a bottom portion positioned in the bottom dielectric layer and on the bottom contact, a lower middle portion positioned on the bottom portion and in the lower middle dielectric layer, a higher middle portion positioned on the lower middle portion and in the higher middle dielectric layer, and a top portion positioned on the higher middle portion and in the top dielectric layer. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

Abstract: Disclosed in the embodiments of the present disclosure are a display panel and a display device. The display panel includes: a display area and a peripheral area surrounding the display area, the display area includes a first display area and a second display area; a plurality of virtual pixel circuits and a plurality of drive pixel circuits, the plurality of virtual pixel circuits are arranged in the peripheral area, and the plurality of drive pixel circuits are arranged in the second display area; the plurality of first light emitting devices are arranged in the first display area, and the plurality of second light emitting devices are arranged in the second display area; the virtual pixel circuit is electrically connected with the first light emitting device, and the drive pixel circuit is electrically connected with the second light emitting device.