Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of first conductive structures positioned on the substrate; a plurality of outer liner layer positioned on sidewalls of the plurality of first conductive structures; and a plurality of bottom inter-feature dielectric layers positioned on the plurality of outer liner layers and between the plurality of first conductive structures. The plurality of outer liner layers include one or more species of vanadium oxide. The plurality of bottom inter-feature dielectric layers are porous.

Abstract: A display panel having a light-transmitting region, at least one first region and a second region includes sub-pixels disposed in the at least one first region and the second region, second light-emitting devices disposed in the light-transmitting region, data lines and first transistors. The data lines include first and second data lines. A first data line is electrically connected to pixel driving circuits in a column of sub-pixels including at least one dummy sub-pixel, and a second data line is electrically connected to pixel driving circuits in a column of sub-pixels in the second region and located in a same column as a column of second light-emitting devices. A second light-emitting device in the column of second light-emitting devices is electrically connected to a pixel driving circuit connected to the first data line. The first data line is electrically connected to the second data line through a first transistor.

Abstract: Embodiments of the present disclosure provide an audio processing method, electronic apparatus and computer-readable storage medium. The method includes: determining a decoding start frame identification and a decoding end frame identification in a preset frame sequence, in which the preset frame sequence includes frame information of audio frames in at least one audio resource, the frame information includes a frame identification, the frame identification includes an audio resource identification and a frame index; acquiring segment data to be decoded in an audio resource associated with a corresponding audio resource identification according to the decoding start frame identification and the decoding end frame identification; and decoding the segment data to be decoded to obtain corresponding target decoded data.

Abstract: A display substrate and a display device. The present display substrate includes a first to a third display region. The first display region includes first pixel repeating units, and allows light from the first side to at least partially penetrate to the second side. The second display region includes second and fourth pixel repeating units. The third display region includes third pixel repeating units. Each first pixel repeating unit is electrically connected to the corresponding fourth pixel repeating unit by means of t transparent connecting traces. The pitch of the first and second pixel repeating units is b1, and the pitch of the third pixel repeating units is b2, the pitch of the transparent connecting traces is D, and the maximum number s of first pixel repeating units in the first direction satisfying s?2*Floor (b1/((D*t))).

Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes a base substrate including a first display region and a second display region. Since pixel circuits for driving light-emitting elements in the second display region are only disposed in the first display region but not disposed in the second display region, the light transmittance of the second display region is ensured to be good. Correspondingly, the display panel in the present disclosure has a good display effect.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a first insulating layer positioned on a substrate; a bottom contact positioned in the first insulating layer; a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer sequentially stacked on the first insulating layer; and a conductive structure including a bottom portion positioned in the bottom dielectric layer and on the bottom contact, a lower middle portion positioned on the bottom portion and in the lower middle dielectric layer, a higher middle portion positioned on the lower middle portion and in the higher middle dielectric layer, and a top portion positioned on the higher middle portion and in the top dielectric layer. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. The interconnection structure has a first lateral surface and a second lateral surface. The first isolation feature is disposed on the first lateral surface of the interconnection structure. The second isolation feature is disposed on the second lateral surface of the interconnection structure. The first isolation feature is different from the second isolation feature.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: Provided are a display panel and a display device. The display panel includes: a base substrate; light-emitting elements including groups of light-emitting elements, at least one group of light-emitting elements including first-region light-emitting elements and second-region light-emitting elements; pixel circuits including groups of pixel circuits, at least one group of pixel circuits including first-type pixel circuits and second-type pixel circuits, at least one second-type pixel circuit is connected with at least one second-region light-emitting element through a conductive line, first light-emitting elements are connected with first pixel circuits through first conductive lines, in the at least one group of light-emitting elements and the at least one group of pixel circuits, first pixel circuits connected with first light-emitting elements are closer to the second display region than each of second pixel circuits connected with second light-emitting elements.

Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.

Abstract: A shift register includes a first control sub-circuit, a second control sub-circuit, a pull-up control sub-circuit and an output control sub-circuit, wherein the first control sub-circuit is configured to provide a signal of a third power supply terminal or a clock signal terminal to a first node and a third node under the control of a signal input terminal, the clock signal terminal and a second node; the pull-up control sub-circuit is configured to provide a signal of a second power supply terminal to the first node under the control of the third node; the second control sub-circuit is configured to provide a signal of the signal input terminal to the second node and a fourth node under the control of the clock signal terminal and the first power supply terminal.

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first initialization circuit and a reset circuit; the first initialization circuit configured to write a first initial voltage into the first end of the driving circuit under the control of an initialization control signal; the reset circuit is configured to write a reset voltage into the second end of the driving circuit or the first end of the driving circuit under the control of a second scan signal; the driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of a control end of the driving circuit.

Abstract: A power supply circuit, a driving method thereof, a printed circuit board, a display module and a display apparatus are disclosed, which relates to a technical field of displaying. The power supply circuit includes a first power management chip and a second power management chip configured to be respectively connected with a display panel and provide different driving signals to the display panel, and the driving signals are configured for driving the display panel to display.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

Abstract: Provided is a display substrate, including a first transparent display region, a second transparent display region and a non-transparent display region. The display substrate includes a plurality of first pixels disposed in an array in the first transparent display region and a plurality of second pixels. The first pixel includes a first light-emitting element and a first pixel circuit. The first pixel circuits in a same row are electrically connected to a same first gate line. The first pixel circuits in a same column are electrically connected to a same first data line. The second pixel includes a second light-emitting element disposed in the second transparent display region and a second pixel circuit disposed outside the first transparent display region and the second transparent display region. The second light-emitting element and the second pixel circuit are electrically connected by a transparent wire.

Abstract: A display substrate and a display apparatus are provided, including a first side for displaying and a second side opposite the first side, a base substrate, a display area, at least one connection line and at least one transfer electrode. Each of the at least one connection line at least partially extends in a first direction and is connected to first power lines respectively connected to adjacent first pixel unit groups in a first display area in the first direction; and each of the at least one transfer electrode at least partially extends in the first direction and is connected to first signal lines that respectively connect to the adjacent first pixel unit groups in the first display area in the first direction, film layers where at least part of the at least one transfer electrode and each of the at least one connection line are located are different.

Abstract: A display substrate includes a base (10) having installation area (Q3), transition area (Q2), and display area (Q1). Sub-pixel areas in the transition area (Q2) include at least first type sub-pixel areas (P) and second type sub-pixel areas (D); sub-pixel areas in the installation area (Q3) include at least third type sub-pixel areas (A); first type sub-pixel areas (P) include pixel circuits; the pixel circuits include driving sub-circuits (20) and light-emitting devices (OLED); second type sub-pixel areas (D) include driving sub-circuits (20); third type sub-pixel areas (A) include OLED; OLED in the third type sub-pixel areas (A) of the installation area (Q3) are coupled to driving sub-circuits (20) in second type sub-pixel areas (D) of transition area (Q2) via signal connection lines (1); and orthographic projections of at least some signal connection lines (1) overlap on base (10).

Abstract: A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.