Abstract: A semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. The first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. The first lower semiconductor structure and the first upper semiconductor structure include different materials. The semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. The first oxide portion has an L-shape.

Abstract: A display substrate comprises a display region comprising a first display sub-region and a second display sub-region adjoining the first display sub-region, a plurality of first-type sub-pixels located in the first display sub-region that are divided into sub-pixel groups, each sub-pixel group comprising at least two adjacent first-type sub-pixels in a row direction, each first-type sub-pixel comprising a light-emitting element and a pixel circuit configured to drive the light emitting element to emit light; and a plurality of power lines connected to the first-type sub-pixels. The power lines comprise first-type and second-type power lines. The first-type power lines extend in the row direction and are connected to pixel circuits of the first-type sub-pixels in the row direction, and the second-type power lines extend in a column direction and are connected to pixel circuits of the first-type sub-pixels in the column direction. The row direction and the column direction intersect.

Abstract: Disclosed is a display panel, including: a base substrate including a first display region, a second display region, and a routing region; a first anode layer, a first light-emitting layer and a first cathode layer disposed in the first display region and sequentially stacked in a direction going away from the base substrate; a second cathode layer, a second anode layer, a second light-emitting layer, and a third cathode layer disposed in the second display area and sequentially stacked in the direction going away from the base substrate, and a first signal transmission layer disposed in the routing region; wherein the first signal transmission layer is connected to the second cathode layer and the first cathode layer, and the first signal transmission layer is further configured to receive a power supply signal.

Abstract: A display substrate includes a driving circuitry, and the driving circuitry includes a first node control circuitry, a second node control circuitry and an output circuitry. The output circuitry is configured to control a driving signal output end to be electrically coupled to a second voltage line under the control of a potential at a first node, and control the driving signal output end to be electrically coupled to a first voltage line under the control of a potential at a second node. Transistors of the output circuitry are arranged at a side of the second voltage line away from a display region, and transistors of the first node control circuitry and transistors of the second node control circuitry are arranged at a side of the transistors of the output circuitry away from the second voltage line.

Abstract: A pixel circuit and a driving method thereof, a display panel, and display device are disclosed. The pixel circuit includes a data writing circuit, a driving circuit, and a compensation circuit. The compensation circuit is connected to a control terminal, a first terminal, and a second terminal of the driving circuit, and is configured to write a compensation voltage based on a first reset voltage into the control terminal of the driving circuit; the data writing circuit is connected to the control terminal of the driving circuit and is configured to write a coupling voltage based on a data voltage into the control terminal of the driving circuit; and the driving circuit is configured to control a driving current for driving a light-emitting element to emit light under control of a voltage applied to the control terminal of the driving circuit.

Abstract: A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second first bottom electrode layer. The semiconductor device further includes a top electrode disposed over and surrounded by the bottom electrode to structure. The top electrode has a ring shape from a top view. In addition, the semiconductor device includes an insulating layer separating the top electrode from the bottom electrode structure.

Abstract: The display substrate includes a drive circuit layer disposed on a base substrate and a light emitting structure layer, the drive circuit layer includes multiple circuit units, multiple first initial signal lines extending along a first direction, and multiple second initial signal lines and low-voltage power supply lines extending along a second direction, the circuit unit includes at least a pixel drive circuit, the light emitting structure layer includes multiple light emitting devices, the first initial signal line is configured to provide an initial voltage signal to the pixel drive circuit, the low-voltage power supply line is configured to provide a low power supply voltage signal to the light emitting device, the second initial signal line is connected to the first initial signal line, and the first initial signal lines and the second initial signal lines constitute a net-like connecting structure.

Abstract: A display substrate includes at least two barrier layers in a peripheral area of the display substrate. The at least two barrier layers includes a first barrier layer forming an enclosure; and a third barrier layer on a side of the first barrier layer closer to a display area. The third barrier layer includes one or more discontinuous portions.

Abstract: A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

Abstract: A display panel, a manufacturing method thereof and a display device. The display panel includes a first region and a second region. The second region includes a driving circuitry layer and a first light-emitting unit located on a base substrate, the first region includes a plurality of second light-emitting units located on the base substrate, the second light-emitting unit is electrically coupled to the driving circuitry layer through a transparent conductive layer, the transparent conductive layer includes at least two conductive sub-layers laminated one on another and insulated from each other, each conductive sub-layer includes at least one transparent conductive line, and each transparent conductive line is coupled to a corresponding second light-emitting unit.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels including a light emitting element and a pixel circuit, the light emitting element includes a second electrode including a main body electrode. The sub-pixels include a first color sub-pixel which includes a first connecting portion. In the first color sub-pixel, the connecting electrode is connected with the first connecting portion through a first via hole, and the first connecting portion is electrically connected with the pixel circuit through a first connecting hole; and the first via hole and the first connecting hole are not overlapped with the main body electrode, and orthographic projections of the first via hole and the first connection hole on a first straight line extending in an extension direction of the data line are overlapped.

Abstract: A display substrate and a display device. The display substrate includes a display region, a first connecting wire and a second connecting wire. The display region includes a first display region and a second display region. The first display region includes a plurality of light emitting devices arranged in an array, and the plurality of light emitting devices includes a first light emitting device and a second light emitting device. The second display region includes a plurality of first pixel circuit units, and the plurality of pixel circuit units includes a first pixel circuit and a second pixel circuit. The first connecting wire is connected to the first pixel circuit and the first light emitting device. The second connecting wire is connected to the second pixel circuit and the second light emitting device. The first direction and the second direction intersect each other.

Abstract: A semi-solid alloy thermal interface composition and method for dissipating heat from an electronic component using the same are disclosed in the present disclosure. The semi-solid alloy thermal interface material comprises, based on total atoms of 100 at. %, 0.1-10 at. % of Bi, 20-30 at. % of In, and 65-75 at. % of Sn. In a method for dissipating heat from an electronic component using the semi-solid alloy thermal interface material, the semi-solid alloy thermal interface material is disposed between a chip and a heat sink, wherein the semi-solid alloy thermal interface material is completely solid at a room-temperature, and has a liquid content ranging from 0.1 to 70 mol % based on a total mole of 100 mol % of the semi-solid alloy thermal interface composition at a temperature of 40 to 130° C.

Abstract: A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second first bottom electrode layer. The semiconductor device further includes a top electrode disposed over and surrounded by the bottom electrode structure. The top electrode has a ring shape from a top view. In addition, the semiconductor device includes an insulating layer separating the top electrode from the bottom electrode structure.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.

Abstract: A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a first insulating layer positioned on a substrate; a bottom contact positioned in the first insulating layer; a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer sequentially stacked on the first insulating layer; and a conductive structure including a bottom portion positioned in the bottom dielectric layer and on the bottom contact, a lower middle portion positioned on the bottom portion and in the lower middle dielectric layer, a higher middle portion positioned on the lower middle portion and in the higher middle dielectric layer, and a top portion positioned on the higher middle portion and in the top dielectric layer. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first impurity region positioned in the substrate; a first dielectric layer positioned on the substrate; a first contact including a buried portion positioned along the first dielectric layer and on the first impurity region, and a protruding portion positioned on the buried portion and protruding from the first dielectric layer; a first top assistant cap covering the protruding portion; and a first top conductive layer positioned on the first top assistant cap. The first top assistant cap includes germanium or silicon germanium.