Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.

Abstract: A display panel and a display apparatus. The display panel comprises a display substrate. The display substrate comprises: a display area (AA) and a binding area (B1) located on one side of the display area; a plurality of sub-pixels (Pxij) located in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels; a plurality of binding pin groups (41) located in the binding area, wherein each binding pin group comprises at least one driving pin group (411) and at least one touch pin group (412), in the plurality of binding pin groups, the plurality of driving pin groups are arranged in a first direction, at least one touch pin group is arranged between the plurality of driving pin groups in an interspersed manner, at least one touch pin group is arranged between every two adjacent driving pin groups.

Abstract: A display substrate and a display device are provided.

Abstract: A method for generating a set of cleanable perimeter segments of an area to be cleaned by a robotic cleaner. Each cleanable perimeter segment defines a path to be followed by the robotic cleaner around an edge of the area to be cleaned. The method includes receiving an occupancy grid map of the area to be cleaned; generating a contiguous accessible area grid map of the area to be cleaned based on the occupancy grid map; determining an outer boundary of each contiguous inaccessible region in the occupancy grid map; and generating the set of cleanable perimeter segments by extracting the outer boundary of each contiguous inaccessible region as a separate perimeter segment. Each perimeter segment includes a plurality of sequential grid elements defining the path to be followed by the robotic cleaner around an edge of the area to be cleaned.

Abstract: The display substrate includes a plurality of circuit units, wherein at least one circuit unit includes a pixel drive circuit, the pixel drive circuit includes a storage capacitor and a plurality of oxide transistors, the storage capacitor includes a first capacitor plate and a second capacitor plate, and a capacitor insulating layer is arranged between the first capacitor plate and the second capacitor plate; and on a plane perpendicular to the display substrate, at least one circuit unit includes a semiconductor layer and a first source-drain metal layer arranged on a base substrate in a direction away from the base substrate, at least one capacitor insulating layer is arranged on a side of the semiconductor layer close to the base substrate, or at least one capacitor insulating layer is arranged on a side of the first source-drain metal layer away from the base substrate.

Abstract: A video encoder and video decoder may determine to enable or disable a template-based inter prediction technique based on whether reference picture resampling or weighted prediction are used. A video encoder and video decoder may determine that a reference picture resampling mode is enabled. determine not to apply a template-based inter prediction technique to the video data based on the reference picture resampling mode being enabled, and code the video data using inter prediction without applying the template-based inter prediction technique.

Abstract: A display substrate and a display device are provided, which includes: a pixel circuit, on the base substrate and including a driving transistor and a storage capacitor; the display substrate includes a first conductive layer, a second conductive layer and a first semiconductor layer, the first conductive layer includes a first connection structure, the first connection structure includes a first end and a second end, the first end is connected with the first semiconductor layer, the second end is electrically connected with a gate electrode of the driving transistor and a first electrode plate of the storage capacitor; the first conductive layer is at a side of the first semiconductor layer away from the base substrate, the second conductive layer is at a side of the first conductive layer away from the base substrate.

Abstract: A display substrate, a manufacturing Method therefor, and a display apparatus are disclosed. The display substrate includes a first display area (100) and a second display area (200), the first display area (100) includes a plurality of first light emitting devices (LD1), a plurality of first circuit units (QD1) and at least one second circuit unit (QD2), and the second display area (200) includes a plurality of second light emitting devices (LD2); the first circuit unit (QD1) includes at least a first anode electrode (51) connected to the first light emitting device (LD1) and a compensation capacitor plate (60) connected to the first anode electrode (51), the compensation capacitor plate (60) is configured to form a compensation capacitor; the second circuit unit (QD2) includes at least a second anode electrode (52), which is connected to the second light emitting device (LD2) through an anode connection line (70).

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: The present invention discloses a method for designing an interference noise of speech based on the human speech structure, including the following steps: (1): obtaining a large amount of speech data containing different speakers and different speech contents, extracting voiceprint information, and then building an initial speech data set; (2): for each user, obtaining a small amount of speech data of the user, extracting voiceprint information, and then matching the most similar speech data in the initial speech data set; (3): performing data augmentation on the matched speech data; (4): segmenting the augmented speech data with a phoneme segmentation algorithm to form a vowel data set and a consonant data set; (5): constructing three noise sequences based on the vowel data set and the consonant data set, and performing superimposition to obtain an interference noise; and (6): continuously generating and playing randomly generated interference noise, and continuously injecting the interference noise into rec

Abstract: The present disclosure provides a pixel circuit, a pixel driving method and a display device. The pixel circuit includes a light-emitting element, a driving circuitry, a first energy storage circuitry, a second energy storage circuitry, a data writing circuitry and a compensation control circuitry. The data writing circuitry writes a data voltage into a second node under the control of a first scanning signal from a first scanning end. The compensation control circuitry controls a first node to be electrically coupled to a second end of the driving circuitry under the control of a second scanning signal from a second scanning end. An effective enabling time period of the second scanning end does not overlap with, and has a length greater than, an effective enabling time period of the first scanning end.

Abstract: A power management integrated circuit (PMIC) soldered onto a printed circuit board, includes: a first output stage circuit and a second output stage circuit. In a separate power supply configuration, first and second current inflow pins of the first and second output stage circuits are soldered to first and second current inflow printed lines, respectively, wherein the first and second current inflow printed lines are not directly electrically connected to each other; and, first and second current outflow pins of the first and second output stage circuits are soldered to first and second current outflow printed lines respectively, wherein the first and second current outflow printed lines are not directly electrically connected to each other. In a cooperation power supply configuration, the first and second current inflow pins are both soldered to a common current inflow printed line of the PCB, to be electrically connected with each other.

Abstract: A driving circuit includes a first node control circuit, a second node control circuit and a first output circuit; the second node control circuit is configured to control to connect the first node and the second node under the control of a low voltage signal provided by the first low voltage input terminal; the first node control circuit is configured to control to connect the first node and the second low voltage input terminal under the control of a first clock signal provided by the first clock signal line; the first output circuit is configured to control to connect the driving signal output terminal and the third low voltage input terminal under the control of a potential of the pull-down node; at least two of the first low voltage input terminal, the second low voltage input terminal and the third low voltage input terminal are different from each other.

Abstract: This disclosure provides a shift register, drive circuit, drive method, display panel, and display apparatus. The shift register includes an input unit, a first control unit, an output unit and an isolation unit, wherein the input unit provides a starting signal of a signal input terminal to a first node, and provides a first signal of a first signal terminal to a second node, so that under control of the second node and a second clock signal terminal, the first control unit provides a second clock signal of the second clock signal terminal to a third node; under control of the third node, the isolation unit provides a voltage signal of the first node to a fourth node; and under control of the fourth node and the third node, the output unit outputs based on the first signal or a second signal of the second signal terminal.

Abstract: A display substrate and a display device are provided, the display substrate includes: a base substrate; a pixel circuit on the base substrate, the pixel circuit includes a storage capacitor including a first electrode plate and a second electrode plate which are opposite to each other; the display substrate further includes a conductive film layer, the conductive film layer includes a first conductive part; the first conductive part includes a main part and a bridge part, the main part corresponds to two second electrode plates, and the bridge part connects the two second electrode plates, and the first conductive part includes a notch between the two second electrode plates, the arrangement of the notch can improve pixel transmittance.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of first conductive structures positioned on the substrate; a plurality of outer liner layer each positioned on a corresponding sidewall of the plurality of first conductive structures; and a plurality of bottom inter-feature dielectric layers positioned on the plurality of outer liner layers and between the plurality of first conductive structures. Each of the outer liner layers includes one or more species of vanadium oxide. The plurality of bottom inter-feature dielectric layers are porous.

Abstract: A display panel, a display device and a manufacturing method thereof, and relates to the field of display technology. The display panel includes: a first display area, provided with a plurality of pixel units; a second display area adjacent to the first display area, which is capable of transmitting light and provided with a plurality of light-emitting device units; a pixel auxiliary area external to the first display area and the second display area, which is provided with a plurality of light-emitting driving units; wherein the light-emitting driving unit is configured to drive the connected light-emitting device unit to emit light.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: a sub-pixel, in a display region and including a light-emitting element, the light-emitting element including a first electrode, a light-emitting layer and a second electrode; a positive power line, connected to the first electrode; a positive power bus, connected to the positive power line; two positive power access ends, at a side of the positive power bus away from a display region, and respectively connected to the positive power bus; a negative power line; an auxiliary electrode, respectively connected to the negative power line and the second electrode; four negative power access ends, at the side of the positive power bus away from the display region, and respectively connected to the negative power line; and a negative power auxiliary line, respectively connected to the negative power access end and the auxiliary electrode.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of first conductive structures positioned on the substrate; a plurality of outer liner layer positioned on sidewalls of the plurality of first conductive structures; and a plurality of bottom inter-feature dielectric layers positioned on the plurality of outer liner layers and between the plurality of first conductive structures. The plurality of outer liner layers include one or more species of vanadium oxide. The plurality of bottom inter-feature dielectric layers are porous.

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes a base substrate including a first display region and a second display region. Since pixel circuits for driving light-emitting elements in the second display region are only disposed in the first display region but not disposed in the second display region, the light transmittance of the second display region is ensured to be good. Correspondingly, the display panel in the present disclosure has a good display effect.