Abstract: A centrifugal testing device for simulating ground subsidence induced by buried pipeline leakage and infiltration includes a model box provided with a transparent observation window at a front side, a chamber partitioning plate, a damaged pipeline model, permeable plates, and a water-soil separation device. A front part of the model box is divided into a test soil chamber for filling model soil and seepage chambers located at two sides of the test soil chamber. A rear part of the model box is divided into a soil filtration chamber and water circulation supply chambers located at two sides of the soil filtration chamber. The damaged pipeline model includes a front end provided with an electric push rod for controlling a crack of the damaged pipeline model to be opened and closed and a rear end provided with a ball valve device and connected to a water pump.

Abstract: The present application discloses a semiconductor device including a substrate; a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate; a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate; and wherein the first threshold voltage is different the second threshold voltage; a thickness of the first insulating stack is different from a thickness of the second insulating stack.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A display may include an array of pixels. A pixel can include an organic light-emitting diode, up to three thin-film transistors, and up to two capacitors. The pixel can include a drive transistor, an emission transistor, and a select transistor. The select transistor can be used to apply a reference voltage to the gate of the drive transistor during a global reset phase and during a global threshold voltage sampling phase and can also be used to apply a data voltage to the gate of the drive transistor during a data programming phase. The drive transistor can receive a power supply voltage that toggles between a low voltage during the global reset phase and a high voltage during other phases of operation. Configured and operated in this way, the pixel need not include separate dedicated anode reset and initialization transistors.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.

Abstract: A method for forming a semiconductor device includes forming a conductive contact over a semiconductor substrate, and forming a first dielectric layer covering the conductive contact. The method also includes partially removing the first dielectric layer to form an opening exposing a top surface of the conductive contact, and forming a bottom electrode covering sidewalls of the opening and the top surface of the conductive contact. The method further includes depositing a second dielectric layer over the bottom electrode using a first process, and depositing dielectric portions over the second dielectric layer and at top corners of the opening using a second process. The first process has a first step coverage, the second process has a second step coverage, and the second step coverage is smaller than the first step coverage. The method includes forming a top electrode covering the second dielectric layer and the dielectric portions.

Abstract: The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.

Abstract: A video decoder can be configured to determine that a current block in a current picture of the video data is coded in an affine prediction mode; determine one or more control-point motion vectors (CPMVs) for the current block; identify an initial prediction block for the current block in a reference picture using the one or more CPMVs; determine a current template for the current block in the current picture; and determine an initial reference template for the initial prediction block in the reference picture; and perform a motion vector refinement process to determine a modified prediction block based on a comparison of the current template to the initial reference template.

Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

Abstract: An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.

Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.

Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Abstract: A vehicle tire cloud computing management system and an application method thereof are provided. A vehicle tire cloud computing management system is formed by combining a vehicle tire management device including tire sensors, a setting tool, and radio frequency identification (RFID) tags with a cloud server, and a car computer. By using the tire sensors to detect tire-related data, and then by outputting the tire-related data to the setting tool, the cloud server, or the car computer for data computation, result judging and/or data storage, so that the function of the tire sensors is more focused on detecting tire conditions, and power consumption of the tire sensors is reduced, while the setting tool, the cloud server, and the car computer are used efficiently to perform computation, management, and application for data related to the tire sensors.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.

Abstract: A display substrate and a display panel are provided.

Abstract: Provided are a display panel and a display device. The display panel includes: a base substrate; light-emitting elements including groups of light-emitting elements, at least one group of light-emitting elements including first-region light-emitting elements and second-region light-emitting elements; pixel circuits including groups of pixel circuits, at least one group of pixel circuits including first-type pixel circuits and second-type pixel circuits, at least one second-type pixel circuit is connected with at least one second-region light-emitting element through a conductive line, first light-emitting elements are connected with first pixel circuits through first conductive lines, in the at least one group of light-emitting elements and the at least one group of pixel circuits, first pixel circuits connected with first light-emitting elements are closer to the second display region than each of second pixel circuits connected with second light-emitting elements.

Abstract: An antenna structure includes a first substrate and a second substrate. The first substrate includes: a semiconductor chip configured to transmit or receive a first radio-frequency (RF) signal; a first ground layer configured to provide ground to the semiconductor chip; and a signal layer arranged on a side of the first substrate opposite to the semiconductor chip and configured to transmit the first RF signal. The second substrate has an antenna array formed of antenna cells, each of the antenna cells including: a first antenna layer configured to radiate second RF signals based on the first RF signal; a second ground layer configured to provide ground to the first antenna layer. The antenna device further includes a plurality of connectors electrically coupling the semiconductor chip to the antenna array.

Abstract: A display substrate. In a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit at least includes a storage capacitor and a plurality of transistors, the plurality of transistors at least includes a driving transistor and at least one switching transistor of a dual-gate structure. In a plane perpendicular to the display substrate, the display substrate includes a plurality of conductive layers, the first polar plate and the gate electrode of the drive transistor are arranged in the same layer, the second polar plate and the first power line are arranged in the same layer.

Abstract: A centrifugal testing device for simulating ground subsidence induced by buried pipeline leakage and infiltration includes a model box provided with a transparent observation window at a front side, a chamber partitioning plate, a damaged pipeline model, permeable plates, and a water-soil separation device. A front part of the model box is divided into a test soil chamber for filling model soil and seepage chambers located at two sides of the test soil chamber. A rear part of the model box is divided into a soil filtration chamber and water circulation supply chambers located at two sides of the soil filtration chamber. The damaged pipeline model includes a front end provided with an electric push rod for controlling a crack of the damaged pipeline model to be opened and closed and a rear end provided with a ball valve device and connected to a water pump.