Patents by Inventor Yao Lin

Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127183
    Abstract: The disclosure relates to the field of information processing, and more particularly to a method, electronic device and storage medium for information processing. According to the embodiments of the disclosure, the method of information processing includes: establishing an association relationship between a first application and a first file, the first application being a program for processing a service processing flow; determining service processing flow information of the first application; and displaying first information corresponding to the service processing flow information at a predetermined position in the first file. The method of information processing provided by the embodiments of the disclosure enables users to conveniently obtain service processing flow information related to the first file through the first file, and facilitates subsequent audit and review of the file or the corresponding service processing flow.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 18, 2024
    Inventors: Changming WANG, Fan YANG, Linna ZHANG, Bingxi LIN, Changyu GUO, Fang LIU, Zisheng LIU, Tian LAN, Fabin LIU, Zhengzhe ZHANG, Siyu HOU, Yao WANG
  • Publication number: 20240125982
    Abstract: A metalens including a transparent substrate and lenses is provided. The lenses are located on the transparent substrate. Each of the lenses includes first columnar microstructures continuously arranged along a first direction and second columnar microstructures continuously arranged along a second direction. A pitch of the first columnar microstructure is different from a pitch of the second columnar microstructure.
    Type: Application
    Filed: November 18, 2022
    Publication date: April 18, 2024
    Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITED
    Inventors: Tzu-Yao Lin, Shih-Chieh Yen
  • Publication number: 20240126724
    Abstract: The disclosure relates to the field of computers, and particularly to a method, apparatus, electronic device and storage medium for information processing. The method of information processing provided in the present disclosure includes: at a time before the end of a service processing flow about a first file, determining a save strategy for the first file in response to a user operation, so that the first file is saved based on the save strategy after the end of the service processing flow.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Changming Wang, Fan Yang, Linna Zhang, Bingxi Lin, Changyu Guo, Fang Liu, Zisheng Liu, Tian Lan, Fabin Liu, Zhengzhe Zhang, Siyu Hou, Yao Wang
  • Publication number: 20240126975
    Abstract: A method of data processing for an application includes displaying service data in a first display area of a first application display interface; displaying first online document information in a second display area of a first application display interface, the first online document carrying a file required for processing the service data; and processing the service data in response to a first operation initiated based on the content carried by the first online document. The method of data processing for an application displays business data and the first online document in the first display area and the second display area respectively, and operates the business data based on the first operation initiated by the content carried by the first online document, so that the processing method of business data is associated with the content carried by the first online document, thereby improving the flexibility and convenience of business data processing.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventors: Changming Wang, Fan Yang, Linna Zhang, Bingxi Lin, Changyu Guo, Fang Liu, Zisheng Liu, Tian Lan, Fabin Liu, Zhengzhe Zhang, Siyu Hou, Yao Wang
  • Publication number: 20240126901
    Abstract: The disclosure provides a method, apparatus, terminal and storage medium for service processing based on an online document. The method includes: determining a first application; establishing an association between the first application and a first online document; and performing a first processing on the first online document according to the information related to the first application. The information processing method provided by embodiments of the present disclosure can process the first online document based on the information related to the first application, so that the data processing of the first online document can adapt to the service logic of the first application itself. While fully utilizing the characteristics of openness and easy collaboration of the online document, the online document can reflect or adapt to the service logic, and improve the flexibility and stability of the service.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Changming Wang, Fan Yang, Linna Zhang, Bingxi Lin, Changyu Guo, Fang Liu, Zisheng Liu, Tian Lan, Fabin Liu, Zhengzhe Zhang, Siyu Hou, Yao Wang
  • Publication number: 20240127182
    Abstract: This disclosure provides a method and apparatus, terminal and storage medium for information processing. The method of information processing includes: receiving a first document for processing a business flow, the business flow comprising one or more business nodes; and when a predetermined operation is performed on a content of the first document, determining an associated person associated with at least one business node of the business flow based on the predetermined operation, and sending a notification message to the associated person.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Changming Wang, Fan Yang, Linna Zhang, Bingxi Lin, Changyu Guo, Fang Liu, Zisheng Liu, Tian Lan, Fabin Liu, Zhengzhe Zhang, Siyu Hou, Yao Wang
  • Patent number: 11961899
    Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
  • Publication number: 20240120294
    Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 11, 2024
    Inventors: Shu-Shen YEH, Chin-Hua WANG, Kuang-Chun LEE, Po-Yao LIN, Shyue-Ter LEU, Shin-Puu JENG
  • Patent number: 11954032
    Abstract: An apparatus for managing buffers and a method thereof are provided. The method for managing buffers includes: receiving a plurality of pieces of data, where the plurality of pieces of data includes a first piece of data and a second piece of data; allocating at least one buffer to establish a cluster buffer according to a data amount of the first piece of data; and if at least one of a first condition and a second condition is satisfied, ending a storage operation of the cluster buffer, where the first condition is that a total remaining space of the at least one buffer that has stored the data in the cluster buffer is less than a remaining space threshold, and the second condition is that the quantity of the at least one buffer that has stored the data in the cluster buffer reaches a cluster threshold.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: April 9, 2024
    Assignee: REALTEK SINGAPORE PRIVATE LIMITED
    Inventors: Mark Tsung-Han Chiang, Mei-Yao Lin
  • Patent number: 11955455
    Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Chien-Sheng Chen, Po-Yao Lin, Po-Chen Lai, Shu-Shen Yeh
  • Patent number: 11955385
    Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
  • Patent number: 11948581
    Abstract: A smart interpreter engine is provided. The smart interpreter engine includes a speech to text converter, a natural language processing module and a translator. The speech to text converter is utilized for converting speech data corresponding to a first language into text data corresponding to the first language. The natural language processing module is utilized for converting the text data corresponding to the first language into glossary text data corresponding to the first language according to a game software. The translator is utilized for converting the glossary text data corresponding to the first language into text data corresponding to a second language.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Gianna Tseng, Shih-Cheng Huang, Shang-Yao Lin, Szu-Ting Chou
  • Patent number: 11948892
    Abstract: A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hao Tsai, Meng-Liang Lin, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng
  • Publication number: 20240107804
    Abstract: A display substrate and a display device are provided. The display substrate includes a display region including light emitting units; the light emitting units are arranged into light emitting unit rows, and the light emitting units in one of the light emitting unit rows are arranged along a first direction; the light emitting units include first light emitting units. In at least part of the display region: distances, in the first direction, between a light emitting region of one first light emitting unit and light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different, and/or distances, in a second direction, between a light emitting region of one first light emitting units and the light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different.
    Type: Application
    Filed: May 31, 2021
    Publication date: March 28, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mingwen WANG, Yao HUANG, Xingliang XIAO, Zhong LU, Yuan CHEN, Yamei ZHOU, Yu SONG, Wei HU, Fuqiang LIN
  • Publication number: 20240105705
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Patent number: 11938678
    Abstract: Disclosed herein are an adhesion blocking element, a three-dimensional printing device and a three-dimensional printing method. The adhesion blocking element comprises: one light-transmittable main body comprising a first surface and a second surface which are disposed opposite to each other, and side faces connecting the first surface and the second surface; and a plurality of microstructures arranged on the main body, wherein each microstructure has one cavity formed in the main body and one first open face which is arranged on the first surface of the main body and communicated to the cavity. The present invention decreases the adhesion between the adhesion blocking element and the cured layer by improving the structure of the adhesion blocking element itself, and eliminates the negative pressure adsorption between the cured layer and the adhesion blocking element, so that it is easier to peel the adhesion blocking element off from the cured layer.
    Type: Grant
    Filed: May 5, 2019
    Date of Patent: March 26, 2024
    Assignee: LUXCREO (BEIJING) INC.
    Inventors: Guang Zhu, Zhifeng Yao, Fang Li, Yi-Ho Lin, Yanhui Guo, Hu Wang
  • Patent number: 11942529
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
  • Patent number: 11942363
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Patent number: 11942396
    Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Shu-Jung Yang, Yu-Min Lin, Chih-Yao Wang, Yu-Lin Chao
  • Publication number: 20240096776
    Abstract: A package substrate is provided and includes a core board body and a first circuit structure and a second circuit structure disposed on opposite sides of the core board body, where the number of wiring layers of the second circuit structure is different from the number of wiring layers of the first circuit structure, so that the package substrate is asymmetrical. The first circuit structure and the second circuit structure are designed according to the thickness and coefficient of thermal expansion of the first dielectric layer of the first circuit structure and the second dielectric layer of the second circuit structure, so as to prevent the problem of warping from occurring to the package substrate.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 21, 2024
    Inventors: Andrew C. CHANG, Min-Yao CHEN, Sung-Kun LIN