Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Abstract: A chiral molecule detector includes a light source, a photodetector, and a carrier. The carrier is configured to reflect at least part of light emitted by the light source to the photodetector. The carrier includes a substrate and a metal reflective layer. An upper surface of the substrate has a periodic hole array containing multiple holes. The metal reflective layer is located on the upper surface of the substrate, and covers a sidewall of the hole and a bottom surface of the hole.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: The present invention relates to a method for dissolving metals by photocatalysis. A metal-containing material to be dissolved is dispersed in a mixed solution of photocatalyst-containing cyanide and organic chloride; then, a photocatalyst is added; next, an oxygen-containing gas or a substance which is capable of generating oxygen is introduced; and irradiation is applied for a period of time to dissolve metals. Compared with the prior method, the present invention is advantageous in moderate reaction condition, energy conservation, environmental protection, low cost, and convenient operation, and is suitable for mass industrial treatment on metal dissolution.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: Resource optimized forwarding of classified requests to different instances of a microservice is provided. The process includes obtaining classified requests to a microservice. The classified requests are classified based on different microservice resource consumption types. Further, the method includes forwarding the classified requests to instances of the microservice with different assigned resource configurations. The forwarding is based on the different microservice resource consumption types of the classified requests.

Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.

Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.

Abstract: Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.

Abstract: A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.