Abstract: 1. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, an etching stop layer, a silicide layer, and a contact metal. The semiconductor substrate has a groove. The dielectric layer and the etching stop layer are disposed in the groove. The silicide layer is located within the semiconductor substrate. The dielectric layer has a via in the groove. The etching stop layer has a through hole under the via of the dielectric layer. The silicide layer is aligned with an inner sidewall of the through hole of the etching stop layer. The contact metal is disposed in the via.

Abstract: Some implementations described herein provide a deposition tool and methods of operation. The deposition tool may be used in the fabrication of integrated circuit devices to deposit materials and/or layers on a semiconductor substrate. The deposition tool may include a chamber (e.g., a processing chamber) that is coated with a dielectric coating on sidewalls of the chamber. The dielectric coating on the sidewalls of the chamber within the deposition tool increases a likelihood of a negative charge accumulating near the sidewalls of the chamber. The increased likelihood of negative charge accumulation near the sidewalls of the chamber may improve a uniformity of an electromagnetic field within the deposition tool (e.g., during a deposition operation) relative to another deposition too not including such a dielectric coating. The improved uniformity of the electromagnetic field may enable an improved uniformity of a material being deposited by the deposition tool to be achieved.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first electrode over a semiconductor substrate. A data storage element is on the first electrode. A second electrode is over the data storage element. A first spacer layer is on a sidewall of the second electrode. A conductive structure is over the second electrode. The conductive structure includes a first segment adjacent to the sidewall of the second electrode. The first segment extends from an upper surface of the first spacer layer to a first sidewall of the first spacer layer.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a phase change material element over a substrate, a first conductive structure, a second conductive structure, a heating structure and a first capping layer. The phase change material element includes a body portion and a surface portion on a top surface of the body portion. A nitrogen concentration of the surface portion is larger than a nitrogen concentration of the body portion. The first conductive structure is physically and electrically connected to the phase change material element. The second conductive structure is physically and electrically connected to the phase change material element. The first conductive structure and the second conductive structure are laterally spaced apart. The heating structure is configured to heat the phase change material structure. The first capping layer is disposed on the surface of the phase change material element.

Abstract: A semiconductor structure includes a bottom electrode, a magnetic tunneling junction stack over the bottom electrode, a top electrode over the magnetic tunneling junction stack, a first dielectric layer under the bottom electrode, a second dielectric layer under the first dielectric layer. The first dielectric layer has a first chemical bond energy and the second dielectric layer has a second chemical bond energy less than the first chemical bond energy.

Abstract: A method of warpage-aware floorplanning for heterogeneous integration structure is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a performing a layout partitioning to divide a layout into a plurality of grids; performing an initial floorplanning by assigning first geometric relations between a plurality of dies such that an effective material of each grid of the plurality of grids is determined; performing a global floorplanning to change the first geometric relations between the plurality of dies to second geometric relations to optimize warpage effect of the heterogeneous integration structure; and performing a detailed floorplanning to determine die order of placement based on material differences between the plurality of dies and an interposer.

Abstract: Some embodiments relate to an integrated circuit (IC) device including a thin-film resistor (TFR) overlying a substrate and including a first film and a second film that are stacked in a direction transverse to a top surface of the substrate. The first film includes a first material having a negative temperature coefficient of resistance (TCR) within a temperature range. The negative TCR causes a resistance of the first film to decrease as a temperature of the first film increases. The second film includes a second material having a positive TCR within the temperature range. The positive TCR causes a resistance of the second film to increase as a temperature of the second film increases.

Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip having an interconnect structure overlying a substrate. The interconnect structure includes a conductive wire disposed in a dielectric structure. The conductive wire comprises a body structure. A passivation structure overlies the interconnect structure. A bond pad overlies the passivation structure. The bond pad comprises an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive wire. The lower bond structures respectively comprise a vertical bond structure and a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Abstract: A diffusion barrier layer is included in a piezoelectric device that includes a plurality of piezoelectric layers. The diffusion barrier layer may be included to trap and/or block lead (Pb) and/or lead oxide (PbOx) from diffusing toward a first piezoelectric layer that occurs during a sol-gel process that used to form a second piezoelectric layer after the first piezoelectric layer formed. Blocking and/or trapping the diffusion of lead (Pb) and/or lead oxide (PbOx) using the diffusion barrier layer may reduce the likelihood of and/or prevent delamination in the piezoelectric device.

Abstract: A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure over a substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A bond pad structure is over the interconnect structure, a first masking layer is over the bond pad structure, and a second masking layer is over the first masking layer. The second masking layer contacts opposing outermost sidewalls of the bond pad structure and the first masking layer. A conductive bump vertically extends through the first masking layer and the second masking layer to contact the bond pad structure.