Abstract: A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.

Abstract: A positioning method and a multi-radar positioning system are provided. In the positioning method, a first object and a second object are detected by a first radar to obtain a first coordinate and a second coordinate on a first coordinate system respectively. The first object and the second object are detected by a second radar to obtain a third coordinate and a fourth coordinate on a second coordinate system respectively. A first candidate coordinate and a second candidate coordinate of the second radar on the first coordinate system are estimated according to the third coordinate and the fourth coordinate. The first candidate coordinate is selected from the first candidate coordinate and the second candidate coordinate as a first radar coordinate of the second radar according to the first coordinate and the second coordinate. The first radar coordinate is output.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure over a substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A bond pad structure is over the interconnect structure, a first masking layer is over the bond pad structure, and a second masking layer is over the first masking layer. The second masking layer contacts opposing outermost sidewalls of the bond pad structure and the first masking layer. A conductive bump vertically extends through the first masking layer and the second masking layer to contact the bond pad structure.

Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A sacrificial layer is formed conforming to the high-k dielectric layer.

Abstract: A semiconductor device that includes a semiconductor substrate, a bottom electrode over the semiconductor substrate, a switching layer over the bottom electrode, a metal ion source layer over the switching layer, and a top electrode over the metal ion source layer. The switching layer includes a compound having aluminum, oxygen, and nitrogen.

Abstract: A phase-change material (PCM) switching device includes: a base dielectric layer; a spreader element disposed in the base dielectric layer, wherein the spreader element extends in a first horizontal direction and comprises: a central portion extending in the first horizontal direction and having a first width in a second horizontal direction perpendicular to the first horizontal direction; a first end portion at a first end of the central portion and having a second width in the second horizontal direction; and a second end portion at a second end of the central portion and having a third width in the second horizontal direction, and wherein at least one of the second width and the third width is larger than the first width; a heater element disposed over the spreader element; a thermal barrier element disposed on the heater element; and a PCM layer disposed on the thermal barrier element.

Abstract: A method for generating a customized WRONoC topology is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing design rules, design specs and a pre-assignment netlist; performing a topology initialization which an initial topology with a minimum number of MRRs is generated according to the netlist; performing a critical path-aware SA optimization to optimize the topology; and performing a wavelength assignment such that the wavelength used by each signal is determined.

Abstract: A method for routing of redistribution layers in IC package is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing design rules, a set of I/O pads and bump pads and a pre-assignment netlist; performing a global routing which generates the guides for any non-acute angle RDL routing; and performing a detailed routing which adjusts the access point for shorter wirelength and finishes the routing. After the access points are located, the nets tile by tile are routed.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first circuit layer, a memory array structure, a bonding layer, a second circuit layer, and a second substrate. The first circuit layer is disposed on the first substrate. The memory array structure is disposed on the first circuit layer. The bonding layer is disposed on the memory array structure. The second circuit layer is disposed on the bonding layer. The second substrate is disposed on the second circuit layer.

Abstract: A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.