Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

Abstract: Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.

Abstract: A unit circuit that constitutes a shift register includes a gate output lowering transistor (T01) whose source terminal is supplied with a second gate low voltage (Vgl2) and a gate output reset transistor (T03) Whose source terminal is supplied with a first gate low voltage (Vgl1), as constituent elements associated with the lowering of gate output. At the time of lowering the gate output, the gate output lowering transistor (T01) is made to be in an on state, and thereafter the gate output reset transistor (T03) is made to be in the on state. In this case, the gate terminal of the gate output reset transistor (T03) is supplied with a scanning signal or a signal having a waveform equivalent to that of the scanning signal outputted from the unit circuit in a subsequent stage.

Abstract: In each unit circuit constituting a shift register, as thin film transistors configured to lower a gate output, a thin film transistor whose state is controlled by a first reset signal and a thin film transistor whose state is controlled by a second reset signal are provided. Then, during the period in which a thin film transistor functioning as a buffer transistor is maintained in an ON state, the first reset signal changes from a low level to a high level, and then the second reset signal changes from a low level to a high level at a timing at which a corresponding gate bus line is to be changed from a selected state to an unselected state.

Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

Abstract: Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.

Abstract: There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.

Abstract: A configuration in which a voltage (a gate on voltage) of only one system is used as a voltage for turning scanning lines to a selected state is employed (single power supply system configuration). A unit circuit that constitutes a shift register within a gate driver includes a thin film transistor whose source terminal is connected to an output control node. In such a configuration, when the external power supply is stopped, a voltage supplied to a gate terminal of the thin film transistor and a voltage supplied to a drain terminal of the thin film transistor are set to the gate on voltage.

Abstract: A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.

Abstract: The present application discloses a scanning signal line drive circuit capable of reducing power consumption and narrowing a picture-frame while ensuring high-speed scanning for image display. First and second gate drivers 410, 420 are arranged to face each other via a display unit 500. Based on a DC buffer method, odd-numbered gate lines are driven by the first gate driver 410 while even-numbered gate bus lines are driven by the second gate driver 420, and when each gate bus line GLi is to be brought into a non-selected state, charges are released from both ends thereof. For this purpose, for example, the end portion of the odd-numbered gate bus line on the first gate driver side is connected to a buffer made up of the activation and inactivation transistors M10, M13L, and the end portion of the odd-numbered gate bus line on the second gate driver side is connected to the inactivation auxiliary transistor M13R.

Abstract: A shift register is implemented that can increase the reliability of long-term operation regarding the driving of gate bus lines over a conventional configuration. The shift register is allowed to operate by clock signals of eight or more phases with an on-duty of less than ½. A stabilization node control portion brings a stabilization node (NB) to an on level for a period less than 50 percent of a normal operation period, based on two or more clock signals among the clock signals of eight or more phases, the stabilization node (NB) being connected to a gate terminal of a thin film transistor that contributes to the drawing of a potential of an output control node (NA) to a VSS potential.

Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.

Abstract: To prevent a decrease in display quality caused when a display apparatus performs pause driving. One end of the n-th scanning signal line (GLn) is connected to the n-th stage circuit (UCn) of a driver circuit. The other end of the n-th scanning signal line is connected to a waveform adjusting circuit (HKn) which adjusts the waveform of the pulse signal of the n-th scanning signal line (GLn) by using a clock signal (CKA) and the pulse signal of the m-th scanning signal line (GLn?1) scanned prior to the n-th scanning signal line.

Abstract: [Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation. [Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.

Abstract: A TFT circuit (101) includes a first node (N1) to which a first low potential (Vc) is supplied, a depression-type first TFT (21) which is arranged between the first node (N1) and low-potential wiring (11) for supplying a second low potential (Va) higher than the first low potential (Vc), and in which a drain terminal is connected to the first node, and a depression-type second TFT (22) which is arranged between the first TFT (21) and the low potential wiring (11) and in which a source terminal is connected to a source terminal of the first TFT, in which the first low potential (Vc) is supplied to a gate terminal of the second TFT, a second node (N2) enterable a floating state is formed between the source terminal of the first TFT and the source terminal of the second TFT, and the second node (N2) is connected to a sub-circuit (SC1) which is settable a potential of the second node (N2) to be lower than the second low potential (Va) and higher than the first low potential (Vc).

Abstract: The present invention provides a monolithic gate driver that includes fewer elements than in conventional configurations. In one aspect, a plurality of stages included in a shift register are divided into a plurality of stage circuit groups, where each stage circuit group includes the stage circuits of P adjacent stages (two stages, for example). Each stage circuit group includes a stabilization node and a stabilization node controller that controls the voltage of the stabilization node. The stabilization node controller includes: thin-film transistors in which the gate terminals thereof are connected to output control nodes, the drain terminals thereof are connected to the stabilization node, and the source terminals thereof are connected to an input terminal for a DC supply voltage; and a thin-film transistor for changing the voltage of the stabilization node to a high level.

Abstract: A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.

Abstract: There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.