Abstract: A display device includes a monolithic gate driver with drive signal trunk wiring lines that transmit drive signals (such as clock signals) made of a source metal in a region on the opposite side of a display region with respect to a shift register region. A VSS trunk wiring line arranged to transmit a low-level direct-current power supply potential is made of a source metal in a region between the shift register region and the display region. Each of bistable circuits defining a shift register and a drive signal trunk wiring line are connected by a drive signal branch wiring line made of a gate metal. Each bistable circuit and the VSS trunk wiring line are connected by a VSS branch wiring line made of a source metal.

Abstract: A gate driver is provided with an odd-numbered stage shift register, an even-numbered stage shift register, and main lines including clock signal main lines. In at least one example embodiment, each stage of one of the shift registers receives the first clock and the second clock from the clock signal main lines, and the third clock and the fourth clock from an adjacently provided stage of the other shift register. Each stage of the shift register can receive the second clock from a different stage of the same shift register. With this, it is possible to reduce a picture-frame area of a panel in a display device provided with a scanning signal line drive circuit having the plurality of shift registers.

Abstract: Stability of a circuit operation in a monolithic gate driver is improved. A bistable circuit is provided with a charge replenishment circuit (71) including: a capacitor (CAP2); a thin-film transistor (MA) having a first electrode supplied with a first clock for charge replenishment (CKA), a second electrode connected to a third-node (N3) connected to one end of the capacitor (CAP2), and a third electrode connected to a second-node (N2) to be maintained at the high level during a normal operation period; and a thin-film transistor (MB) having a first electrode supplied with a second clock for charge replenishment (CKB), a second electrode supplied with a high-level DC power supply potential (VDD), and a third electrode connected to the third-node (N3).

Abstract: Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.

Abstract: The purpose of this invention is to increase reliability of a switching element while reducing consumption power. In the vertical blanking period, an end pulse signal (ED) changes from the low level to the high level. The potential of first nodes (N1) in the first stage to (m?1)th stage of cascade-connected m-stage bistable circuits included in a shift register of the scanning signal drive circuit is reliably maintained at the low level, and the potential of second nodes (N2) in the first stage to the (m?1)th stage changes from the high level to the low level. In a bistable circuit in the m-th stage, the potential of the first node (N1) in the m-th stage changes from the high level to the low level, and the potential of the second node (N2) in the m-th stage is maintained at the low level. The supply to a bistable circuit of clock signals (CKA, CKB) is stopped.

Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.

Abstract: A peripheral region of a display panel includes a signal distribution device (4) for time-dividing and distributing, to output terminals (7), an output signal from a source driver. The signal distribution device (4) includes switching elements (20) for the output terminals (7). Each switching element (20) is controlled by a selection signal supplied to a control line (9) connected with a gate electrode. Each switching element (20) includes a source electrode and the drain electrode each having a comb-like shape having a stem part and branch parts extending therefrom. In at least one switching element (20), only all of or part of the branch parts overlap the control line (9) and a semiconductor layer (10). This suppresses abnormal heat generation of a source driver in a display device including the signal distribution circuit by which an output signal from the source driver is distributed to pixels in time series.

Abstract: There is realized a scanning signal line drive circuit (in a display device) capable of, even in a case where a circuit in a shift register is formed using a thin-film transistor which is relatively large in off leakage, suppressing unnecessary power consumption due to a leakage current in the thin-film transistor. In at least one embodiment, bistable circuit that forms the shift register includes a thin-film transistor for raising a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin-film transistor, another thin-film transistor for lowering a potential of the region netA, and a region netB connected to a gate terminal of the other thin-film transistor. With this configuration, the potential of the region netB is raised based on a third clock which is advanced in phase by 90 degrees with respect to the first clock and is lowered based on a fourth clock which is delayed in phase by 90 degrees with respect to the first clock.

Abstract: A display device of at least one embodiment of the present invention has a connection changeover circuit, including switch elements for time-division driving, formed on a liquid crystal panel, and the switch elements are paired so that two switch elements in each pair are connected in parallel to one video signal line. The paired switch elements are turned on at the same time, and immediately before one of the switch elements is turned off upon completion of a charging period for its corresponding video signal line, only the other switch element is turned off. As a result, while maintaining drive performance, it is possible to solve the impact of fieldthrough phenomenon caused by one of the switch elements, which are transistors, and also reduce parasitic capacitance formed in the other switch element, thereby suppress the impact of fieldthrough phenomenon caused by that switch element.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: A bistable circuit includes an input terminal (41) for a set signal, an input terminal (42) for a reset signal, an output terminal (48) for a state signal, a thin-film transistor (M2) for increasing a potential of the output terminal (48) based on a first clock, a thin-film transistor (M1) for increasing a potential of a first-node connected to a gate terminal of the thin-film transistor (M2) based on the set signal, a thin-film transistor (M5) for decreasing the potential of the first-node, a thin-film transistor (M7) for increasing a potential of a second-node connected to a gate terminal of the thin-film transistor (M5) based on the reset signal, a thin-film transistor (M6) for decreasing the potential of the output terminal (48) based on the potential of the second-node, a thin-film transistor (M3) for increasing the potential of the second-node based on the set signal, and a capacitor (CAP2) having one end connected to the second-node and the other end connected to the input terminal (41).

Abstract: It is an object to realize a gate driver that can cause a scanning signal to quickly fall after a charge period in each row ends. A gate driver is configured by two shift registers. In an n-th stage bistable circuit (SR(n)) in an entire shift register (410), a region netA connected to a gate terminal of a thin-film transistor that increases a potential of an output node for outputting a state signal (Q) based on a first clock (CKA) is set to an on level based on the state signal (Q) outputted from an (n?2)-th stage bistable circuit (SR(n?2), the region netA is set to an off level based on the state signal (Q) outputted from an (n+2)-th stage bistable circuit (SR(n+2)), and the output node is set to an off level based on the state signal (Q) outputted from an (n+3)-th stage bistable circuit (SR(n+3)).

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: In a monolithic gate driver, a power consumption is reduced as compared with a conventional one without lowering a voltage of a scanning signal to be applied to a gate bus line as compared with a conventional one. A stage constituent circuit includes first-node to third-node, a thin-film transistor (M7) that changes a potential of a scanning signal toward a VDD potential when a potential of the first-node is in a HIGH level, a thin-film transistor (M6) that changes a potential of a different stage control signal toward a potential of a clock (CKA) when a potential of the second-node is in the HIGH level, a capacitor (C1) that is disposed between the first-node and the second-node, and a capacitor (C2) that is disposed between the second-node and the third-node.

Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.

Abstract: Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.

Abstract: Stability of a circuit operation in a monolithic gate driver is improved. A bistable circuit is provided with a charge replenishment circuit (71) including: a capacitor (CAP2); a thin-film transistor (MA) having a first electrode supplied with a first clock for charge replenishment (CKA), a second electrode connected to a third-node (N3) connected to one end of the capacitor (CAP2), and a third electrode connected to a second-node (N2) to be maintained at the high level during a normal operation period; and a thin-film transistor (MB) having a first electrode supplied with a second clock for charge replenishment (CKB), a second electrode supplied with a high-level DC power supply potential (VDD), and a third electrode connected to the third-node (N3).

Abstract: In a display device including a monolithic gate driver, without degrading display quality, miniaturization is achieved while reducing power consumption. Drive signal trunk wiring lines (71) that transmit drive signals such as clock signals are formed from a source metal (701) in a region on the opposite side of a display region with respect to a shift register region. A VSS trunk wiring line (73) for transmitting a low-level direct-current power supply potential is formed from a source metal (701) in a region between the shift register region and the display region. Each of bistable circuits forming a shift register (410) and a drive signal trunk wiring line (71) are connected by a drive signal branch wiring line (72) formed from a gate metal (702). Each bistable circuit and the VSS trunk wiring line (73) are connected by a VSS branch wiring line (74) formed from a source metal (701).

Abstract: A bistable circuit includes an input terminal (41) for a set signal, an input terminal (42) for a reset signal, an output terminal (48) for a state signal, a thin-film transistor (M2) for increasing a potential of the output terminal (48) based on a first clock, a thin-film transistor (M1) for increasing a potential of a first-node connected to a gate terminal of the thin-film transistor (M2) based on the set signal, a thin-film transistor (M5) for decreasing the potential of the first-node, a thin-film transistor (M7) for increasing a potential of a second-node connected to a gate terminal of the thin-film transistor (M5) based on the reset signal, a thin-film transistor (M6) for decreasing the potential of the output terminal (48) based on the potential of the second-node, a thin-film transistor (M3) for increasing the potential of the second-node based on the set signal, and a capacitor (CAP2) having one end connected to the second-node and the other end connected to the input terminal (41).

Abstract: It is an object to realize a gate driver that can cause a scanning signal to quickly fall after a charge period in each row ends. A gate driver is configured by two shift registers. In an n-th stage bistable circuit (SR(n)) in an entire shift register (410), a region netA connected to a gate terminal of a thin-film transistor that increases a potential of an output node for outputting a state signal (Q) based on a first clock (CKA) is set to an on level based on the state signal (Q) outputted from an (n?2)-th stage bistable circuit (SR(n?2), the region netA is set to an off level based on the state signal (Q) outputted from an (n+2)-th stage bistable circuit (SR(n+2)), and the output node is set to an off level based on the state signal (Q) outputted from an (n+3)-th stage bistable circuit (SR(n+3)).