Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.

Abstract: Each stage (Xi) of a shift register includes a first output transistor (M5), a first capacitor (C1), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), and a fourth switching element (M6).

Abstract: A peripheral region of a display panel includes a signal distribution device (4) for time-dividing and distributing, to output terminals (7), an output signal from a source driver. The signal distribution device (4) includes switching elements (20) for the output terminals (7). Each switching element (20) is controlled by a selection signal supplied to a control line (9) connected with a gate electrode. Each switching element (20) includes a source electrode and the drain electrode each having a comb-like shape having a stem part and branch parts extending therefrom. In at least one switching element (20), only all of or part of the branch parts overlap the control line (9) and a semiconductor layer (10). This suppresses abnormal heat generation of a source driver in a display device including the signal distribution circuit by which an output signal from the source driver is distributed to pixels in time series.

Abstract: A shift register of at least one embodiment of the present invention is a shift register supported by an insulative substrate, wherein: the shift register includes a plurality of stages each sequentially outputting output signals; each of the plurality of stages includes a first transistor for outputting the output signals, and a plurality of second transistors whose source region or drain region is electrically connected to a gate electrode of the first transistor; and the plurality of second transistors include a multi-channel transistor having an active layer including at least two channel regions, a source region and a drain region. This improves characteristics of a shift register forming a monolithic gate driver.

Abstract: A display device of at least one embodiment of the present invention has a connection changeover circuit, including switch elements for time-division driving, formed on a liquid crystal panel, and the switch elements are paired so that two switch elements in each pair are connected in parallel to one video signal line. The paired switch elements are turned on at the same time, and immediately before one of the switch elements is turned off upon completion of a charging period for its corresponding video signal line, only the other switch element is turned off. As a result, while maintaining drive performance, it is possible to solve the impact of fieldthrough phenomenon caused by one of the switch elements, which are transistors, and also reduce parasitic capacitance formed in the other switch element, thereby suppress the impact of fieldthrough phenomenon caused by that switch element.

Abstract: There is realized a scanning signal line drive circuit (in a display device) capable of, even in a case where a circuit in a shift register is formed using a thin-film transistor which is relatively large in off leakage, suppressing unnecessary power consumption due to a leakage current in the thin-film transistor. In at least one embodiment, bistable circuit that forms the shift register includes a thin-film transistor for raising a potential of an output terminal based on a first dock, a region netA connected to a gate terminal of the thin-film transistor, another thin-film transistor for lowering a potential of the region netA, and a region netB connected to a gate terminal of the other thin-film transistor. With this configuration, the potential of the region netB is raised based on a third clock which is advanced in phase by 90 degrees with respect to the first clock and is lowered based on a fourth clock which is delayed in phase by 90 degrees with respect to the first clock.

Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Abstract: There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Abstract: A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Abstract: A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states 1, 2, . . .

Abstract: A semiconductor memory device including (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundant

Abstract: A semiconductor memory device includes a controller programming a nonvolatile memory cell by applying a first pulse so that a charge amount smaller than a target charge amount is accumulated in the nonvolatile memory cell, a second pulse train so that a second charge amount smaller than the target charge amount and larger than the first charge amount is accumulated in the nonvolatile memory cell, and a third pulse train so that a third charge amount falling within an allowable error range of the target charge amount is accumulated. The semiconductor memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and memory functional units formed on both sides of the gate electrode.

Abstract: A semiconductor memory device includes: a plurality of nonvolatile memory cells; a first load cell for generating a read voltage relative to a read current during reading from a selected nonvolatile memory cell; a reference cell for storing a reference state corresponding to a reference current of the selected nonvolatile memory cell; a second load cell for generating a voltage based on the reference current through the reference cell; and a programming circuit for generating a reference voltage equal to a voltage obtained from a specific current-voltage characteristic of the first load cell with respect to the reference current and programming the reference cell so as to equalize the voltage of the second load cell with the reference voltage, thereby to compensate for variations in the first load cell.

Abstract: A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane.

Abstract: A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references respectively corresponding to first and second voltages; applying a programming voltage to the memory cell; sensing a threshold voltage level of the memory cell; and comparing the sensed threshold voltage level with the first and second references and, in the case where the threshold voltage level is higher than the first reference and lower than the second reference, indicating that the memory cell is programmed into the desired state, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region formed below the gate electrode, a source and a drain as diffusion regions formed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of re

Abstract: A semiconductor storage device is provided with a gate electrode, a semiconductor layer, a gate insulating film sandwiched between the gate electrode and the semiconductor layer, a channel region under the gate electrode, diffusion regions provided respectively on two sides of the channel regions and being of the other conductivity region than the channel region, memory elements 1 provided respectively on two sides of the gate electrode and having a function of holding charges, and a word line driver circuit, in which the CMOS technique is used. The driver circuit includes a common node for supplying a potential for activating an output inverter for driving a row word line. While the semiconductor storage device is in a read mode, a CMOS inverter other than the output inverter controls a signal at the common node, the CMOS inverter connected to a read input line.

Abstract: There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.