Patents by Inventor Yasuhiko Kurosawa

Yasuhiko Kurosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220229725
    Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, reading a codeword from a non-volatile memory, decoding the codeword to obtain at least input data, determining validity of the input data using a first signature after processing the input data through a data path, and in response to determining that the input data is valid using the first signature, sending the input data to a host.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Applicant: Kioxia Corporation
    Inventors: Ofir Kanter, Avi Steiner, Yasuhiko Kurosawa
  • Publication number: 20220199183
    Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: Kioxia Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa, Neil Buxton
  • Publication number: 20220075562
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.
    Type: Application
    Filed: March 3, 2021
    Publication date: March 10, 2022
    Applicant: Kioxia Corporation
    Inventors: Yasuhiko KUROSAWA, Naomi TAKEDA, Masanobu SHIRAKAWA, Yasuyuki USHIJIMA, Shinichi KANNO
  • Patent number: 11211950
    Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 28, 2021
    Assignee: Kioxia Corporation
    Inventors: Kuminori Hyodo, Kenji Sakurada, Yasuhiko Kurosawa, Takashi Nakagawa
  • Publication number: 20210373784
    Abstract: A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.
    Type: Application
    Filed: March 12, 2021
    Publication date: December 2, 2021
    Applicant: Kioxia Corporation
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA
  • Patent number: 11183259
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 23, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa
  • Publication number: 20210211142
    Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.
    Type: Application
    Filed: September 14, 2020
    Publication date: July 8, 2021
    Applicant: Kioxia Corporation
    Inventors: Kuminori HYODO, Kenji SAKURADA, Yasuhiko KUROSAWA, Takashi NAKAGAWA
  • Patent number: 10884706
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa, Yohei Koganei, Yuji Nagai
  • Patent number: 10878898
    Abstract: A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n?3). The first circuit is configured to calculate an estimated value of each of n?m determination voltages based on values of m determination voltages (2?m?n?1) among the n determination voltages, and calculate a difference between a value of each of the n?m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n?m determination voltages.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryo Sekiguchi, Shingo Yanagawa, Yasuhiko Kurosawa, Eriko Akaihata
  • Publication number: 20200301602
    Abstract: A nonvolatile memory includes a memory array, a sensor for measuring a temperature, an interface through which a write command is to be received, and a control circuit. The control circuit is configured to write information of the temperature measured by the sensor in a data storing area of the memory array in which user data associated with the write command is not capable of being written into, when writing the user data in the memory array in response to the received write command.
    Type: Application
    Filed: August 28, 2019
    Publication date: September 24, 2020
    Inventor: Yasuhiko KUROSAWA
  • Publication number: 20200265910
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Kioxia Corporation
    Inventors: Avi STEINER, Hanan WEINGARTEN, Yasuhiko KUROSAWA
  • Patent number: 10658058
    Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiko Kurosawa, Avi Steiner, Hanan Weingarten
  • Patent number: 10643730
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa
  • Publication number: 20200090742
    Abstract: A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n?3). The first circuit is configured to calculate an estimated value of each of n?m determination voltages based on values of m determination voltages (2?m?n?1) among the n determination voltages, and calculate a difference between a value of each of the n?m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n?m determination voltages.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 19, 2020
    Inventors: Ryo SEKIGUCHI, Shingo YANAGAWA, Yasuhiko KUROSAWA, Eriko AKAIHATA
  • Publication number: 20200004505
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA, Yohei KOGANEI, Yuji NAGAI
  • Patent number: 10459691
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa, Yohei Koganei, Yuji Nagai
  • Patent number: 10430101
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa
  • Patent number: 10366770
    Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiko Kurosawa, Avi Steiner, Hanan Weingarten
  • Publication number: 20180210654
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA
  • Patent number: 10018673
    Abstract: According to one embodiment, a semiconductor device comprises an integrated circuit having a plurality of current modes different in operation current; a voltage sensor that detects a voltage in use by the integrated circuit; a BIST control circuit that generates BIST patterns different in the operation current and creates a flag indicating the success or failure of a BIST corresponding to the operation current based on the result of detecting the voltage while the integrated circuit is made to operate based on the BIST pattern; and a storing unit that stores the flag. The integrated circuit sets the current mode based on the flag.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiko Kurosawa