Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.

Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of configuration objects according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.

Abstract: Systems and methods for increasing the efficiency of communications between master devices and slave devices in a system. A master normally sends a command to a slave if a token from the slave is received. Determining whether a token is of the correct type requires multiple processing cycles. Alternatively, if all of the slaves have available buffer slots, an “all token available” signal is asserted. When the “all token available” signal is received, the master can send any command without having to decode any of the tokens.

Abstract: Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a cache replacement manager determines in which of n possible entries data will be replaced. The cache replacement manager is configured to take into account whether each cache entry is defective when determining whether to select that entry as the destination entry for new data. The cache manager unit may implement a least-recently-used policy in selecting the cache entry in which the new data will be replaced. The cache replacement manager then treats any defective entries as if they hold the most recently used data, and thereby avoids selecting defective entries as the destination for new data. In one embodiment, the cache performs index translation before indexing into each set of cache entries in order to effectively redistribute defective entries among the indices.

Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of configuration objects according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.

Abstract: Multi-processor system including processors, a host-PCI bridge, and other devices which are connected to each other by a processor bus and a clock control bus for clock frequency adjustment. Each of the processors, a host-PCI bridge, and other devices operate in synchronism with others based on clocks generated by incorporated clock generation circuits. Each of the processors, a host-PCI bridge, and other devices dynamically execute clock frequency changing operations to the incorporated clock generation circuits by using at least the clock control bus in synchronism with others. Thus, the frequencies of clocks generated by each of the processors, a host-PCI bridge, and other devices can be dynamically changed in synchronism with others.

Abstract: A cache flush unit has an MF RAM and an MBT Tag RAM. The MBT Tag RAM stores address information, associated with modified blocks of caches of all processors, in entries in units of cache lines. The MF RAM stores, as information to be used to search for an index of one of the entries on the MBT Tag RAM, which contains an address of at least one modified block, data having a value obtained by ORing modified bits of all processors in the entries together with the index. In cache flush, the address of the modified block can be read out quickly by using the information stored in the MF RAM.

Abstract: A memory controller provided on a multiprocessor system has a scoreboard used to manage the progress of memory access operations (the operating state of access instructions) and reduces the overhead in executing synchronization at a high level of execution priority. The scoreboard holds synchronization flags set in response to the acceptance of synchronization as well as the operation codes and addresses of the accepted access instructions. The memory controller sets a synchronization flag at the time when it has accepted a synchronizing instruction from the processor, and then resets the synchronization flag after the execution of the synchronizing operation has been completed.